Eigenpair computation is fundamental in machine learning and signal processing but faces$\mathbf {O(n^{3})}$complexity and data movement limits on digital platforms. Resistive random-access memory (RRAM)-based analog matrix computing (AMC) offers a low-latency, in-memory alternative, enabling$\mathbf {O(1)}$matrix operations by encoding matrices as conductance and exploiting circuit laws. Previous AMC eigenvector circuit can compute the dominant eigenvector but requires prior knowledge of the corresponding eigenvalue, and is incapable of solving for all eigenpairs. This work introduces an approach that decomposes eigenpair computation into matrix inversion task and eigenvalue determination by sweeping, enabling two RRAM-based AMC circuit designs: the modified-INV circuit for dominant eigenpair computation and the modified-GINV circuit for all eigenpairs computation. Applied to principal component analysis, the modified-GINV circuit generated principal components for the Iris dataset and extracted eigenfaces for image reconstruction —both closely matching the theoretical values. Moreover, we investigated the impact of non-ideal factors, including RRAM device variation, operational amplifier input offset voltage, and interconnect resistance, as well as power consumption, providing valuable guidance for evaluating circuit performance.

In-memory analog matrix computing (AMC) with resistive random-access memory (RRAM) represents a highly promising solution that solves matrix problems in one step. However, the existing AMC circuits each have a specific connection topology to implement a single computing function, lack of the universality as a matrix processor. In this work, we design a reconfigurable AMC macro for general-purpose matrix computations, which is achieved by configuring proper connections between memory array and amplifier circuits. Based on this macro, we develop a hybrid system that incorporates an on-chip write-verify scheme and digital functional modules, to deliver a general-purpose AMC solver for various applications.

Recently, in-memory analog matrix computing (AMC) with nonvolatile resistive memory has been developed for solving matrix problems in one step, e.g., matrix inversion of solving linear systems. However, the analog nature sets up a barrier to the scalability of AMC, due to the limits on the manufacturability and yield of resistive memory arrays, non-idealities of device and circuit, and cost of hardware implementations. Aiming to deliver a scalable AMC approach for solving linear systems, this work presents BlockAMC, which partitions a large original matrix into smaller ones on different memory arrays. A macro is designed to perform matrix inversion and matrix-vector multiplication with the block matrices, obtaining the partial solutions to recover the original solution. The size of block matrices can be exponentially reduced by performing multiple stages of divide-and-conquer, resulting in a two-stage solver design that enhances the scalability of this approach. BlockAMC is also advantageous in alleviating the accuracy issue of AMC, especially in the presence of device and circuit non-idealities, such as conductance variations and interconnect resistances. Compared to a single AMC circuit solving the same problem, BlockAMC improves the area and energy efficiency by 48.83% and 40%, respectively.

Knowledge base entity typing from the description text (KBET-X) has become an important research direction, which takes semantically richer descriptive text as input to obtain better typing results. However, existing approaches either consider all sentences in the text but ignore the entities themselves or consider only the sentences in which the entities are mentioned without considering the other sentences in the text. To address these issues, we propose a novel framework for KBET-X based on an entity-aware heterogeneous graph attention network that makes full use of all sentences in the description text and considers the entities themselves. Specifically, we construct a heterogeneous graph for the description text with the node being a word or sentence. Node embeddings are initialized with an entity-aware encoder. Then we use a context encoder to obtain a contextual node representation of each word and sentence, consisting of a heterogeneous graph attention network and a gated recurrent unit (GRU) network. Finally, we use a type decoder based on a multilayer perceptron (MLP) network to obtain the types of each entity. Experiments conducted on the DBpedia dataset show that our method achieves the new state-of-the-art performance. We also conduct an ablation study to demonstrate that each component plays an essential role in our framework.

Analog matrix computing (AMC) with resistive memory implies naturally massive parallelism and in-memory processing, thus representing a promising solution for accelerating data-intensive workloads in many applications. In AMC circuits, the interconnect resistances residing in the crosspoint resistive arrays arise as a main non-ideal factor degrading the computing accuracy. Simulating and optimizing the circuits are of fundamental importance for large system integration. In this work, we develop a physics-based iterative algorithm to quickly model the matrix-vector multiplication (MVM) operation of crosspoint resistive array with interconnect resistances, thus quadratically reducing the time complexity of circuit simulation. In addition, we propose a new MVM circuit for matrix with negative values, in parallel with the conventional column-wise splitting (CS) and row-wise splitting (RS) circuits. The circuit is based on the conductance compensation (CC) strategy to realize a simplified RS scheme. The discrete Fourier transform (DFT) is implemented using this circuit as a case study. Simulation results reveal that the computing error caused by interconnect resistances is remarkably reduced in the CC-RS circuit. Also, the CC-RS scheme is demonstrated to be more immune to device variations and source/sink resistances. Our results provide an efficient modeling method together with an optimized approach for AMC circuits with non-idealities.

The increasing demand for data-intensive computing applications, such as artificial intelligence (AI) and more specifically machine learning (ML), raises the need for novel computing hardware architectures capable of massive parallelism in performing core algebraic operations. Among the new paradigms, in-memory computing (IMC) with analogue devices is attracting significant interest for its large-scale integration potential, together with unrivaled speed and energy performance. Here, we present a fully-analogue, universal primitive capable of executing linear algebra operations such as regression, generalized least-square minimization and linear system solution with and without preconditioning. We study the impact of the main circuit parameters on accuracy and bandwidth with analytical closed-form expressions and SPICE simulations. Scaling challenges due to parasitic resistance/capacitance and their impact on key parameters such as bandwidth and accuracy are discussed. Finally, a comparison with existing solvers belonging to the same IMC framework is made to assess advantages and disadvantages of the proposed circuit.

Recently, an in-memory analog circuit based on crosspoint memristor arrays was reported, which enables solving linear regression problems in one step and can be used to train many other machine learning algorithms. To explore its potential for computing accelerator applications, it is of fundamental importance to improve the computing speed of the circuit,i.e., the circuit response towards correct outputs. In this work, we comprehensively studied the transfer function of this circuit, resulting in a quadratic eigenvalue problem that describes the distribution of poles. The minimal real part of non-zero eigenvalues defines the dominant pole, which in turn dominates the response time. Simulations for multiple linear regression solutions with different datasets evidence that, the computing time does not necessarily increase with problem size. The dominant pole is related to parameters in the circuit, including feedback conductance, and gain bandwidth products of operational amplifiers. By optimizing these parameters synergistically, the dominant pole shifts to higher frequencies and the computing speed is consequently optimized. Our results provide a guideline for design and optimization of in-memory machine learning accelerators with analog memristor arrays. Also, issues including power consumption, impact of noise and variation of sources and memristors are investigated to offer a comprehensive evaluation of the circuit performance.

The purpose of this study is to develop an eBooks learning system perceived usefulness and perceived ease of use survey for elementary school students. The sample of this study includes 6672 students (age 6-12) in China who have experience using eBooks learning system. The results indicate that students, in general, believe using eBooks would enhance their Learning performance but it is not easy to use. Ebooks experience show a significant effect on the perceived usefulness. It is found that students with more experience of using the eBooks tend to have higher scores on the scale of perceived usefulness.