The explosive growth of the Internet of Things (IoT) has ushered in an era of smart, interconnected devices yet with it comes an urgent need for robust and efficient security. IoT devices often operate under severe constraints, including limited processing power, memory, and energy resources making traditional cryptographic solutions impractical. This has fueled the rise of lightweight cryptography (LWC), a new frontier of algorithms tailored to deliver strong security without compromising performance. Among the standout candidates, Ascon has emerged as the primary recommendation for lightweight authenticated encryption in the final round of the prestigious CAESAR competition (Competition for Authenticated Encryption: Security, Applicability, and Robustness). At the heart of Ascon lies a complex permutation process involving round constants, substitution boxes (S-boxes), and a linear diffusion layer components that demand optimized hardware design. This paper introduces novel S-box implementation techniques for FPGA platforms, pushing the boundaries of existing 5-bit hardware designs. Our approach not only improves efficiency but also secure, high-performance cryptographic systems in the age of pervasive IoT.

The multiply-accumulate (MAC) unit performs multiplication and accumulation, which makes it an essential component for digital signal processing (DSP) applications. Designing high-performance MAC units is crucial for enhancing the computational efficiency of modern computer systems. However, achieving a balance between delay, power consumption, and area utilization poses a significant challenge. This study thoroughly compares and analyzes various multiplier and adder architectures, including Vedic multipliers, ripple carry adders, Brent-Kung adders and pipelined BrentKung adders. The research aims to design an efficient MAC unit by investigating optimal combinations of these components. The proposed design utilizes a Vedic Multiplier using Brent-Kung adder and Pipeline Brent-Kung adder which are compared with other configurations. The MAC unit is implemented in Verilog HDL and analyzed using Intel Quartus Prime and functionally verified using Intel ModelSim. The design was implemented on the Altera Cyclone V 5CSXFC6D6F31I7ES FPGA. The synthesis process reveals that the proposed design achieves a low delay of 28.506 ns, an area utilization of 360 LUT units, and a balanced power consumption of 427.600 mW, resulting in the speed of$\mathbf{3 1 0. 8 5 0 ~ M H z}$. The study concludes that combining the Vedic multiplier with Brent-Kung adder and Pipeline BrentKung adder significantly improves MAC unit performance.

The logarithmic number system has been proposed as an alternative to floating-point arithmetic. Multiplication, division and square-root operations are accomplished with inexpensive fixed-point methods, but addition and subtraction are considerably more challenging. Recent work has demonstrated that these operations too can be done with similar speed and accuracy to their FP equivalents, but the necessary circuitry is complex. In particular, it is dominated by the need for large ROM tables for the storage and interpolation of non-linear functions. We describe a new co-transformation procedure that eliminates much of the ROM space and allows the easy synthesis of the remainder in logic, and we then evaluate several interpolation methods that might benefit from it. Synthesised 32-bit implementations are compared with floating-point units, and show substantial reductions in delay, with equivalent accuracy and area.

The logarithmic number system has been proposed as an alternative to floating-point arithmetic. Multiplication, division and square-root operations are accomplished with fixed-point methods, but addition and subtraction are considerably more challenging. Recent work has demonstrated that these operations too can be done with similar speed and accuracy to their FP equivalents, but the necessary circuitry is complex. In particular, it is dominated by the need for large ROM tables for the storage of non-linear functions. This paper describes two algorithms, a new co-transformation procedure and an improvement to an existing interpolation method, that reduce these tables to an extent that allows their easy synthesis in logic. An implementation shows substantial reductions in area and delay from the previous best 32-bit realisation, with equivalent accuracy.