Capacitor sizing is a crucial step when designing charge-scaling digital-to-analog converters (DACs). Larger capacitor size can achieve better circuit accuracy and performance due to less impact from process gradient, parasitic mismatch, and local variation. However, it also results in larger chip area and higher power consumption. The size of binary-weighted capacitors in charge-scaling DACs is highly sensitive to the routing parasitics. Unmatched routing parasitics among binary-weighted capacitors will lead to large capacitor size for satisfying circuit accuracy and performance. Previous work focuses on the study of generating high-quality common-centroid placement of unit capacitor arrays while ignoring routing parasitics. None of them address the sizing of binary-weighed capacitors. This paper presents the first problem formulation in the literature which simultaneously considers capacitor sizing and parasitic matching during common-centroid capacitor layout generation such that the power consumption is minimized while the circuit accuracy/performance is also satisfied. Experimental results show that the proposed approach can achieve very significant chip area and power reductions compared with the state-of-the-art approaches.

Capacitor sizing is a crucial step when designing a charge-scaling digital-to-analog converter. Larger capacitor size can achieve better circuit accuracy and performance due to less impact from random, systematic, and parasitic mismatch. However, it also results in much larger chip area and even more power consumption. In addition to minimizing random and systematic mismatch during common-centroid capacitor placement, this paper presents the first problem formulation in the literature which simultaneously considers capacitor sizing and parasitic matching during common-centroid capacitor layout generation such that the power consumption is minimized while the circuit accuracy/performance is also satisfied. Experimental results show that the proposed approach can achieve very significant chip area and power reductions compared with the state of the art.

In analog layout design, the accuracy of capacitance ratios correlates closely with both the matching properties among the ratioed capacitors and the induced parasitics due to interconnecting wires. However, most of the previous works only emphasized the matching properties of a common-centroid placement, but ignored the induced parasitics after it is routed. This paper addresses the parasitic issue in addition to device matching during common-centroid capacitor layout generation. To effectively minimize the routing-induced parasitics, a novel common-centroid placement style, distributed connected unit capacitors, is presented. Based on the placement style, the ratioed capacitor layout generation flow and algorithms are proposed to simultaneously optimize the matching properties of a common-centroid placement and minimize the induced parasitics. Experimental results show that the proposed approach can greatly reduce area, wirelength, and routing-induced parasitics, and guarantee the best matching quality after routing.