This paper presents an efficient methodology for FPGA arithmetic design based on Boolean function optimization. Focusing on constant multiplication, modular multiplication and reduction, and division by constants, the proposed approach achieves up to 20× LUT reduction and up to 50% delay improvement compared to Vivado-generated designs. Experimental results also demonstrate competitive area–delay trade-offs relative to FloPoCo, highlighting the effectiveness of the method for high-performance FPGA arithmetic implementations.

This paper proposes a method for hardware integer division by a constant, based only on combinational logic, i.e. without requiring storage and feedback in calculations. The proposed scheme for division consists of adders and encoders, where encoders are systems of Boolean functions. The proposed divisor provides at the output the quotient and the residue (at the same time or separately). Experiments conducted on FPGA demonstrate up to three times improvement in area cost compare to the optimized divisor circuits provided by the Xilinx tools, while the delay is improved by 25% for dividends with less than 48-bit. It is also shown in this paper that the proposed approach is scalable, and in comparison to the state-of-the-art, the proposed approach improves the area or the delay, or both for many constant values and input bit sizes.

Arithmetic operations, such as addition, multiplication, division and modular division, impact on the quality of arithmetic logic units and of the whole processor, with respect to area and delay of the circuit, power consumption, testability. In this article we propose an algorithm to implement efficiently the operation of modular division (X (mod P)), where P is pre-selected. The proposed approach is based on splitting the input operands into smaller binary tuples and then minimizing in parallel the two-level form of each suboperation on the tuples of the decomposition. The experiments show gains in performance and area of our approach vs. to circuits synthesized by state-of-art EDA tools with an advantage in delay and area up to 30 times.