Mechanisms to explicitly manage the presence of data in caches are fundamental for the correctness and performance of modern systems. These operations, while critical, often incur significant performance penalties even when carefully used. Moreover, these mechanisms are implemented in proprietary and often undocumented hardware, so research into optimizations and novel designs is mostly limited to slow, simplified software simulations. In this paper, we design microarchitectural extensions to support two types of user-controlled cache writebacks to main memory. Furthermore, we propose Skip It, a mechanism built on top of our extensions that substantially reduces redundant writebacks. We implemented these designs on the open-source BOOM out-of-order RISC-V CPU. The performance in hardware is ≈ 100 cycles which favorably compares to similar operations in commercially available server-class platforms. In addition, Skip It performs as well as or better than state-of-the-art software techniques for avoiding unnecessary writebacks.

Function as a Service (FaaS) and the associated serverless computing paradigm alleviates users from resource management and allows cloud platforms to optimize system infrastructure under the hood. Despite significant advances, FaaS infrastructure still leaves much room to improve performance and resource efficiency. We argue that both higher performance and resource efficiency are possible --- while maintaining secure isolation --- if we are willing to revisit the FaaS programming model and system software design. We propose Dandelion, a clean-slate FaaS system that rethinks the programming model by treating serverless functions as pure functions, thereby explicitly separating computation and I/O. This new programming model enables a lightweight yet secure function execution system. It also makes functions more amenable to hardware acceleration and enables dataflow-aware function orchestration. Our initial prototype of Dandelion achieves 45× lower tail latency for cold starts compared to Firecracker. For 95% hot function invocations, Dandelion achieves 5× higher peak throughput.

Hybrid computing platforms, comprising CPU cores and FPGA logic, are increasingly used for accelerating data-intensive workloads in cloud deployments, and are a growing topic of interest in systems research. However, from a research perspective, existing hardware platforms are limited: they are often optimized for concrete, narrow use-cases and, therefore lack the flexibility needed to explore other applications and configurations.

Modern computer server systems are increasingly managed at a low level by baseboard management controllers (BMCs). BMCs are processors with access to the most critical parts of the platform, below the level of OS or hypervisor, including control over power delivery to every system component. Buggy or poorly designed BMC software not only poses a security threat to a machine, it can permanently render the hardware inoperative. Despite this, there is little published work on how to rigorously engineer the power management functionality of BMCs so as to prevent this happening. This article takes a first step toward putting BMC software on a sound footing by specifying the hardware environment and the constraints necessary for safe and correct operation. This is best accomplished through automation: correct-by-construction power control sequences can be efficiently generated from a simple, trustworthy model of the platform’s power tree that incorporates the sequencing requirements and safe voltage ranges of all components. We present both a modeling language for complex power-delivery networks and a tool to automatically generate safe, efficient power sequences for complex modern platforms. This not only increases the trustworthiness of a hitherto opaque yet critical element of platform firmware: regulator and chip power models are significantly simpler to produce than hand-written power sequences. This, combined with model reuse for common components, reduces both time and cost associated with platform bring-up for new hardware. We evaluate our tool using a new high-performance 2-socket server platform with >100W per socket TDP, tight voltage limits and 25 distinct power regulators needing configuration, showing both fast (<10s) tool runtime, and correct power sequencing of a live system.

This article describes the development of a software architectural framework for implementing compute-aware control systems, where the term “compute-aware” describes controllers that can modify existing low-level computing platform power managers in response to the needs of the physical system controller. This level of interaction means that high-level decisions can be made as to when to operate the computing platform in a power-savings mode or a high-performance mode in response to situation awareness of the physical system. The framework is demonstrated experimentally on a mobile robot platform. In this example, a situation-aware governor is developed that adjusts the speed of the processor based on the physical performance of the robot as it traverses a path through obstacles. The results show that the situation-aware governor results in overall power savings of up to 38.9 percent with 1.3 percent degradation in performance compared to the static high-power strategy.

In-memory database management systems (DBMSs) outperform disk-oriented systems for on-line transaction processing (OLTP) workloads. But this improved performance is only achievable when the database is smaller than the amount of physical memory available in the system. To overcome this limitation, some in-memory DBMSs can move cold data out of volatile DRAM to secondary storage. Such data appears as if it resides in memory with the rest of the database even though it does not.

This paper introduces a software policy for memory management in heterogeneous memory systems in order to improve the trade-offs between performance and power consumption, while attempting to make the best use of different characteristics of the underlying memory technologies. In this policy, the operating system and the application co-schedule page management in order to make informed decisions about page allocation and migration. Software-Controlled 2- Level Memory (Soft2LM) is a hardware-agnostic approach for efficient usage of heterogeneous memory that allows for region-based allocations, migrations, and application advice. We include analysis of the access characteristics of the PARSEC 3.0 suite of benchmarks, both as motivation for software-guided intelligent page placement as well as for understanding where application advice can make a difference. Our evaluation running PARSEC on our Soft2LM Linux kernel shows an average 4.7x improvement over comparable RAMDISK- based swapping. Even when migrating 100 and 1000 pages per second between regions, Soft2LM performs comparably to a stock system with twice the available DRAM, showing a 1.8\% and 0.7\% improvement, respectively.

There are numerous ways to control power usage of modern systems. Dynamic voltage and frequency scaling (DVFS) and C- and P-states are commonly available in hardware, and operating systems have fine-grained control of these states. Unfortunately, most DVFS systems simply consider CPU utilization when determining which P-state to enter. Running average power limit (RAPL), introduced by Intel in their Sandy Bridge line of processors, allows researchers and system designer to obtain detailed estimates of energy consumption by the core, uncore and DRAM. In this paper we use Linux's perf_events subsystem to measure a number of commonly cited performance metrics while running the SPEC CPU2006 benchmarks in addition to calculating average power using RAPL registers. This paper shows initial promising results correlating DRAM memory consumption to stall-cycle ratio.

With trends in mixed-signal systems-on-chip indicating increasingly extreme scaling of device dimensions and higher levels of integration, the tasks of both design and device validation is becoming increasingly complex. Post-silicon validation of mixed-signal/RF systems provides assurances of functionality of complex systems that cannot be asserted by even some of the most advanced simulators. We introduce RAVAGE (from “random;” “validation;” and “generation”), an algorithm for generating stimuli for post-silicon validation of mixed-signal systems. The approach of RAVAGE is new in that no assumption is made about any design anomaly present in the DDT; but rather, the stimulus is generated using the DUT itself with the objective of maximizing the effects of any behavioral differences between the DUT (hardware) and its behavioral model (software) as can be seen in the differences of their response to the same stimulus. Stochastic test generation is used since the exact nature of any behavioral anomaly in the DUT cannot be known a priori. Once a difference is observed, the model parameters are tuned using nonlinear optimization algorithms to remove the difference between its and the DUT's responses and the process (test generation→tuning) is repeated. If a residual error remains at the end of this process that is larger than a predetermined threshold, then it is concluded that the DUT contains unknown and possibly malicious behaviors that need further investigation. Experimental results on an RF system (hardware) are presented to prove feasibility of the proposed technique.