We propose a new replay snapshotting (RS) technique for strategy learning from past matches in real-time strategy game StarCraft: Brood War (SCBW).It allows for more precise understanding of particular strategy aspects by sampling the state of selected game features at important checkpoints during a match.We use RS to extract and refine a set of strategies from a large replay dataset STARDATA.To validate our approach in a competitive environment, we implement an AI agent for SCBW.It is able to perform the extracted strategy set against opponents in the BASIL Ladder competition.The agent consistently achieves rank C with 56 % win rate which is a significant improvement over our previous approaches.

Real-time strategy games are popular in AI research and education.Among them, Starcraft: Brood War (SCBW) is particularly well known.Recently, the largest known SCBW game replay dataset STARDATA was published.We classify player strategies used in the dataset for all 3 playable races and all 6 match-ups.We focus on early to mid-game strategies in matches less than 15 minutes long.By mapping the classified strategies to replay files, we label the files of the dataset and make the labeled dataset available.

Real-time strategy games are currently very popular as a testbed for AI research and education.StarCraft: Brood War (SC:BW) is one of such games.Recently, a new large, unlabeled human versus human SC:BW game replay dataset called STARDATA was published.This paper aims to prove that the player strategy diversity requirement of the dataset is met, i.e., that the diversity of player strategies in STARDATA replays is of sufficient quality.To this end, we built a competitive SC:BW agent from scratch and trained its strategic decision making process on STARDATA.The results show that in the current state of the competitive environment the agent is capable of keeping a stable rating and a decent win rate over a longer period of time.It also performs better than our other, simple rule-based agent.Therefore, we conclude that the strategy diversity requirement of STARDATA is met.

Segmentation is the key computer vision task in modern medicine applications.Instance segmentation became the prevalent way to improve segmentation performance in recent years.This work proposes a novel way to design an instance segmentation model that combines 3 semantic segmentation models dedicated for foreground, boundary and centroid predictions.It contains no detector so it is orthogonal to a standard instance segmentation design and can be used to improve the performance of a standard design.The presented custom designed model is verified on the Gland Segmentation in Colon Histology Images dataset.

Built-in self-repair (BISR) concept is widely utilized and proven by industry to increase the reliability of regular structures such as memory cores. The idea of using this concept in mostly irregular structures such as logic cores is quite new and represents a challenging task with many problems involved; e.g. the identification of regular parts in a logic core suitable for reconfiguration, excessive area overhead and complexity of reconfiguration logic, etc. Current promising solutions for an efficient BISR architecture design are based on reconfigurable logic blocks (RLBs). In this paper, a new automated generator of the adequate BISR reconfiguration architecture is proposed. The generation process input is a simple description of arbitrary logic core already divided into RLBs and the generated output is the synthesizable HDL description of the BISR architecture for the core.

Ever smaller nanotechnologies introduce new types of defects and fault mechanisms with negative influence on system on-chips (SoCs) reliability and operational life. This paper presents a fault diagnosis and repair procedure which is implemented into generic built-in self-repair architecture. The procedure utilizes on-line fault detection whereas repair is performed during off-line mode. Experimental results show quicker repair process and area overhead which is well below the additional area of triple modular redundancy system.

Built-in self-repair (BISR) approach utilized mostly in regular structures of memory cores has been a promising approach to increase the reliability of any type of integrated circuit. BISR considers spare blocks which in the case of a fault occurrence are used to replace defected circuit parts. A new fault detection and repair procedure with a generic BISR architecture for logic cores is presented in this paper. The architecture is able to localize and repair multiple faults (both permanent and transient), to identify faulty functional blocks, to detect faulty backup blocks, and to repair the core function by employing backup blocks if possible. The number of repairable faults is determined by the number of reconfigurable logic blocks (RLBs) in the core. The whole repair procedure needs only 4 test runs. Experimental results show an additional area of approximately 140% which is still within acceptable level compared to other redundant methods (TMR overhead is 200% without the voter area).

The built-in self-repair (BISR) concept is utilized and proven by industry mainly in regular structures of system-on-chips (SoCs) memory cores. On the other hand, the idea of self repair concept for logic cores introduced and developed in several papers is relatively new, as the irregular structure of these types of cores represents a serious limitation. However, there is a need of a complex BISR architecture that can be widely used on different types of logic cores in order to support further the reliability of SoCs. This paper presents a generic BISR architecture based on reconfigurable logic blocks (RLBs) applicable for any logic core inside a SoC together with in detail defined basic requirements guiding the architecture development and also algorithms handling fault detection and localization procedure.

Built-in self-repair (BISR) is widely used to repair embedded memories within system on a chip (SoC) designs to improve their yield. One key component of the BISR circuit responsible for allocating redundancies is the redundancy analysis (RA) algorithm. One of the most important parameters used to evaluate RA algorithms is repair rate (the ratio of the number of the repaired memories to the number of faulty memories). In most BISR designs, redundancies are used on the row/column level. Some approaches target the block-based architecture where both memories and redundancies are divided into several blocks. Thus, allocation can be done on the block level and is more effective in terms of repair rate. These approaches, however, cannot guarantee optimal repair rate. In this paper, we propose a redundancy analysis algorithm for bit-oriented memories with block-based redundancy architecture with optimal repair rate.