Guanglong Li

dblp:133/3317 · DBLP profile ↗
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1ranked-venue papers
1as first author
1since 2021 · last 2024
0009-0005-0073-130XORCID · reported

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-author · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Hardware accelerators and domain-specific architectures · 48% Interconnection networks and networks-on-chip · 48% GPUs and heterogeneous computing · 5%

Topics — the 6 heaviest of 7, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Hardware accelerators and domain-specific architectures › accelerator integration
chiplet-based accelerator
0.812024
HPPI: A High-Performance Photonic Interconnect Design for Chiplet-Based DNN Accelerators · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2024
Hardware accelerators and domain-specific architectures
dataflow mapping
0.812024
HPPI: A High-Performance Photonic Interconnect Design for Chiplet-Based DNN Accelerators · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2024
Hardware accelerators and domain-specific architectures › machine learning accelerator
DNN accelerator
0.812024
HPPI: A High-Performance Photonic Interconnect Design for Chiplet-Based DNN Accelerators · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2024
Interconnection networks and networks-on-chip
optical interconnection networks
0.812024
HPPI: A High-Performance Photonic Interconnect Design for Chiplet-Based DNN Accelerators · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2024
Interconnection networks and networks-on-chip
optical network-on-chip
0.812024
HPPI: A High-Performance Photonic Interconnect Design for Chiplet-Based DNN Accelerators · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2024
Interconnection networks and networks-on-chip › interconnect architecture
reconfigurable interconnect
0.812024
HPPI: A High-Performance Photonic Interconnect Design for Chiplet-Based DNN Accelerators · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2024

Methods — techniques the papers use, named apart from their topics

communication-aware optimization · 0.8backpropagation neural network · 0.8
YearPublicationVenuePosition
2024 HPPI: A High-Performance Photonic Interconnect Design for Chiplet-Based DNN Accelerators
abstract
In pursuit of higher inference accuracy, the complexity and parameter size of recent deep neural networks (DNNs) have increased significantly. Due to the increasing demand for computing power, the chiplet-based accelerator has been an important computing platform that can handle these DNN models more efficiently. In widely used DNN models, the feature sizes and the number of channels vary greatly among different convolutional layers. Existing chiplet-based accelerators typically adopt consistent optimization strategy for all of the convolutional layers regardless of their sizes, which would limit the inference performance. In this work, we carry out communication-aware customized optimization for convolutional layers with different sizes. First, we propose a reconfigurable high-performance photonic interconnect (HPPI) architecture to facilitate the communication in chiplet-based DNN accelerators. Second, we propose a customized dataflow as the mapping framework and provide four communication patterns of the photonic interconnect with different ways of spatial mapping. Third, we propose a lightweight back propagation neural network to efficiently select the optimal communication pattern for each convolutional layer. The proposed photonic interconnect can be switched between the four communication patterns to enable communication-aware customized optimization for each convolutional layer in the DNN model. As compared to Simba (a representative chiplet-based accelerator with electronic interconnect), HPPI reduces the execution time by 72.23% on average, while saving the energy consumption by 25.49% on average. As compared to ASCEND (a state-of-the-art chiplet-based accelerator with photonic interconnect), HPPI reduces the execution time by 34.04% on average, while saving the energy consumption by 10.34% on average.
Guanglong Li, Yaoyao Ye
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.1