Abstract Deep neural networks (DNNs) have delivered unprecedented achievements in the modern Internet of Everything society, encompassing autonomous driving, expert diagnosis, unmanned supermarkets, etc. It continues to be challenging for researchers and engineers to develop a high-performance neuromorphic processor for deployment in edge devices or embedded hardware. DNNs’ superpower derives from their enormous and complex network architecture, which is computation-intensive, time-consuming, and energy-heavy. Due to the limited perceptual capacity of humans, accurate processing results from DNNs require a substantial amount of computing time, making them redundant in some applications. Utilizing adaptive quantization technology to compress the DNN model with sufficient accuracy is crucial for facilitating the deployment of neuromorphic processors in emerging edge applications. This study proposes a method to boost the development of neuromorphic processors by conducting fixed-point multiplication in a hybrid Q-format using an adaptive quantization technique on the convolution of tiny YOLO3. In particular, this work integrates the sign-bit check and bit roundoff techniques into the arithmetic of fixed-point multiplications to address overflow and roundoff issues within the convolution’s adding and multiplying operations. In addition, a hybrid Q-format multiplication module is developed to assess the proposed method from a hardware perspective. The experimental results prove that the hybrid multiplication with adaptive quantization on the tiny YOLO3’s weights and feature maps possesses a lower error rate than alternative fixed-point representation formats while sustaining the same object detection accuracy. Moreover, the fixed-point numbers represented by Q(6.9) have a suboptimal error rate, which can be utilized as an alternative representation form for the tiny YOLO3 algorithm-based neuromorphic processor design. In addition, the 8-bit hybrid Q-format multiplication module exhibits low power consumption and low latency in contrast to benchmark multipliers.

Next-generation industrial edge artificial intelligence (AI) applications will undoubtedly emerge on energy-efficient, highly-integrated platforms incorporating various sensors, processors, and functional modules. Embedding the data quantization module onto edge AI chips, connecting sensors, processors, and functional modules is critical to achieving adaptive transformation of diverse data representation formats. This paper proposes a novel adaptive and low-power quantization technique and systematically validates its effectiveness from algorithm to hardware module for industrial IoT applications, covering precise navigation for autonomous vehicles and accurate classification utilizing deep neural networks (DNNs). The proposed quantization method merges an adaptive conversion function from floating-point to fixed-point binaries and an adaptive radix-point determination function, ensuring adequate resolution and minimal error loss of the fixed-point inputs to the edge AI modules. The experimental results demonstrate that the quantization error in the proposed quantization technique contributes negligible errors to the navigation solutions of the strapdown inertial navigation system and the DNNs' top-1 and top-5 classification accuracy (on the order of 10$^{-8}$and 10$^{-7}$). Moreover, a quantization-on-multiplier (QoM) hardware module is designed, synthesized, and routed in accordance with the proposed quantization technique. The simulation results indicate that the QoM's power consumption and area are 0.1 mW and 649.552$\mu \text{m}^{2}$, accounting for 5% and 14.15% of its total energy consumption and area, respectively. With our proposed on-chip quantization technique, the time required to quantize the parameters of DNNs is up to 1142 times shorter than with the existing benchmark off-chip quantization approaches.

A hybrid signed convolution module with the architecture of an unsigned divide-and-conquer (UDC) multiplier is proposed to improve the functional diversity and energy efficiency of artificial intelligence (AI) accelerators based on spin-transfer-torque magnetic random access memory (STT-MRAM). The proposed UDC multiplier framework enables three multiplication modes ($n \times n$,$n \times n$/2, and$n/2\times n$/2 bit), considerably enhancing the multiplier’s versatility for next-generation AI accelerators. Compared to the state-of-the-art convolution accelerators, the UDC multiplier-based convolution module offers the lowest average power consumption for$8\times8$bit convolution. By deploying power-gating technology on STT-MRAM, the proposed convolution module preserves sufficient accuracy in high-bit multiplication while decreasing energy consumption by a factor of 22. Furthermore, incorporating a hybrid convolution module improves power efficiency by an additional$8\times $, culminating in a$175\times $decrease in power efficiency for an STT-MRAM-based AI accelerator.

In the above article[1], the reference numbers [10], [11], [12], and [13] inTable IIwere not correct and should be changed to [11], [12], [13], and [14]. The correctTable IIis illustrated as follows.

Offloading the unprecedented growing data to the edge exhibits a mainstream trend in the Industrial Internet of Things (IIoT) era, delivering far-reaching impacts in all aspects of our daily lives, including transportation, health care, and entertainment. However, voluminous data analyzes and processing at the edge will unavoidably raise the edge processor's burden and dramatically expand its design complexity and energy dissipation. This article proposes a flexible bit-adjustment-based energy-efficient convolution module with an approximate divide-and-conquer (ADC) multiplier for compact and low-power edge processor design. The maximum distribution search technique is utilized to exploit the optimal fixed-point representation format for both input and output of the convolution module. The neural network manifests the same precision as a 32-b floating-point multiplication deploying the determined representation formats. An ADC multiplier is proposed to realize the convolution module by eliminating the high-bit multiplication between weights and feature maps. The dynamic power consumption of the ADC multiplier-based convolution module with the$Q(6, 9)$input and$Q(7, 8)$output representation formats is 3.85% lower than that of the 16-b signed multiplication circuit. Furthermore, the dynamic power consumption with$Q(6, 9)$input is capable of being decreased by 15.38% for the 16-b convolution if the output is represented by the$Q(1, 14)$format and by up to 39.93% for the 64-b multiplication. The practical verification system of the convolution module working on a field-programmable gate array evaluation board exhibits an outstanding low-power characteristic.

Nonvolatile spintronic devices have potential advantages, such as fast read/write and high endurance together with back-end-of-the-line compatibility, which offers the possibility of constructing not only stand-alone RAMs and embedded RAMs that can be used in conventional VLSI circuits and systems but also standby-power-free high-performance nonvolatile CMOS logic employing logic-in-memory architecture. The advantages of employing spintronic devices, especially magnetic tunnel junction (MTJ) devices with CMOS circuits, are discussed, and the current status of the MTJ-based VLSI computing paradigm is presented along with its prospects and remaining challenges.

A nonvolatile associative memory architecture based on the Magnetic Tunnel Junction (MTJ) devices has been proposed for high-speed low-power recognition. In order to reduce the power dissipation without sacrificing the speed performance, an intelligent power-saving scheme has been developed taking the advantage of non-volatility of MTJ devices. The power lines of 4-Transistor 2-MTJ nonvolatile memory cells are controlled by not only word line signals but also the internal power control signals supplied from the data-mask/power-gating units to only activate the currently accessed memory elements. The proof-of-concept chip for 128-dimension data vectors has been designed under a 90-nm 5-metal CMOS/MTJ hybrid technology, and the chip operation at 100MHz has been verified by SPICE simulation. Compared to the conventional 6T-SRAM architecture, the proposed architecture achieves the higher speed and up to 97% power reduction. Moreover, this architecture is also proved to be particularly suitable for the applications with higher dimension data vectors.