Ricardo Venieris

dblp:133/8235 · also Ricardo Almeida Venieris · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 2013
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Software engineering, systems software and programming languages · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Software engineering, system software, and programming languages
1 paper
Software testing · 100%

Topics — the 2 heaviest of 2, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Software testing
model-based testing
0.212013
RSA-MBT: a test tool for generating test artifacts based on models · ESEC/SIGSOFT FSE 2013
Software testing
test artifact generation
0.212013
RSA-MBT: a test tool for generating test artifacts based on models · ESEC/SIGSOFT FSE 2013

Methods — techniques the papers use, named apart from their topics

model-driven engineering · 0.2
YearPublicationVenuePosition
2013 RSA-MBT: a test tool for generating test artifacts based on models
abstract
Model-Based Testing (MBT) has attracted the attention of many industries and, hence, it has provided several approaches reported in the literature. The Software Engineering Lab (LES) at the Pontifical Catholic University of Rio de Janeiro has worked extensively on coordinating and carrying out tests of large-scale software systems developed (for web and desktop) for different domains (e.g. petroleum, e-commerce, etc). Based on this experience, an LES test group created a new test modeling language called UML Testing Profile for Coordination (UTP-C) to model relevant test data. However, to use the advantages of the new modeling, an appropriate test-modeling tool became necessary. Thus, this paper presents the RSA-MBT, a new plug-in developed for the Rational Software Architecture (RSA) tool, to generate a set of test artifacts from UTP-C diagrams.
Andrew Diniz da Costa, Ricardo Venieris, Gustavo R. de Carvalho, Carlos José Pereira de Lucena
ESEC/SIGSOFT FSE2