ABSTRACT With the rapid advancement of generative artificial intelligence, large language models (LLMs) have become increasingly integrated into education, particularly for automated formative feedback and writing assessment. This study introduces and evaluates an AI‐driven intelligent feedback system aimed at promoting sustainable and inclusive practices in higher education. It does so by delivering cost‐effective feedback in under‐resourced contexts and adaptive guidance for diverse learners. The system is built on transformer‐based models (BERT and RoBERTa) to support personalised writing evaluation and feedback generation. The system aims to improve students’ self‐assessment accuracy (SAA), a critical factor for self‐regulated learning, while addressing the challenge of delivering high‐quality feedback efficiently in under‐resourced contexts. A quasi‐experimental design was employed to examine the effects of LLM‐generated feedback (LLMF) on students’ SAA and to investigate how these effects vary by initial ability. Results indicated no significant group‐level difference in posttest SAA between the experimental and control groups. More importantly, interaction analysis revealed a significant moderating effect of Initial Self‐Assessment Accuracy (ISAA). Students with lower baseline accuracy benefited substantially from LLMF, while those with higher baseline SAA showed limited change. This compensatory effect highlights the potential of LLMF to reduce inequities in self‐regulated learning. These findings demonstrate the potential of AI‐driven feedback systems to cost‐effectively reduce calibration gaps and foster metacognitive development. By embedding adaptive and personalised mechanisms, such systems advance educational equity and promote scalable personalised learning. They also contribute to the broader agenda of intelligent and sustainable education.

Packet classification is a key mechanism that classifies incoming packets into flows to enable software-defined networking as well as a variety of networking services. Currently, ternary content addressable memory (TCAM) has been widely used for high-speed and low-latency packet classification. However, both range expansion and update performance are the fundamental issues for TCAM-based packet classification. A rule containing ranges could be replicated to multiple rules after converting its ranges into prefixes or ternary strings to occupy more than one TCAM entry. Many range encoding algorithms have been proposed to alleviate or avoid the problem of range expansion. These algorithms can be classified into database-independent (DI) and database-dependent (DD). While database-independent algorithms can accommodate new ranges without re-encoding the existing ranges, they may still cause rule replication. In contrast, database-dependent algorithms could avoid rule replication by adaptively encoding ranges, but new ranges may result in updates of the existing ranges. Accordingly, both types of algorithms may multiply the cost of TCAM updates. In this paper, we propose a DD range-encoding algorithm, Longest Enclosure Prefix Range Encoding (LEPRE), which can ensure that any new range does not cause any rule replication and re-encoding of the existing ranges. LEPRE employs the original fields as a part of range encoding to significantly decrease the requirements of extra bits for range encoding. Our experiment results show that LEPRE can maximize the TCAM storage efficiency. LEPRE also fully supports incremental updates to minimize the latency of TCAM updates.

This paper presents a wide-voltage-range, fast-transient all-digital buck converter using a high-resolution digital pulsewidth modulator (DPWM). The converter employs the multithreshold-voltage band-control technique to shorten its transient response. The DPWM uses an all-digital delay-locked loop (ADDLL) to control its cycle. The usage of ADDLL leads to the DPWM possessing a small area while maintaining high cycle resolution. Moreover, the proposed ADDLL-based cyclecontrolled DPWM can achieve synchronization between its input and output. This decreases the loop delay of the proposed converter so that the system is easy to be stabilized. The prototype chips of both the ADDLL-based cycle-controlled DPWM and the all-digital buck converter are fabricated in 0.35-μm CMOS process. Measurement results of the cyclecontrolled DPWM show that the duty cycle of its output is adjustable from 1% to 99% in a 0.78% increment per step when operating at 1 MHz. The measured transition time of the all-digital buck converter is <;3.5 μs when the load current changes from 50 to 500 mA, and vice versa.

In recent years, task placement technology for reconfigurable FPGA has been developed into 2-D arrays. In this paper, we propose a methodology to pre-place hardware resource into multi-area to achieve the high utilization of hardware resource and reduce used area. The method solves the task type placement problems on the partial dynamic reconfigurable systems. The proposed placement method can provide multi reconfigurable area reusable which depends on each request to load corresponding reconfigurable module into pre-place reconfigurable area. In this experiment, the task placement into the configuration area is using by the tool of Xilinx Plan Ahead 14.1 [15] to analyze and verify on the Xilinx Virtex-6 system development platform. Comparison of related work, the experiment results shown that the proposed placement methodology increases 20.1% the utilization of hardware resources and reduces 61.1% the area of hardware resources.