Radiation-induced multiple bit upsets (MBUs) are a major reliability concern in nanoscale technology nodes. Occurrence of such errors in the configuration frames of a field-programmable gate array (FPGA) device permanently affects the functionality of the mapped design. Periodic configuration scrubbing combined with a low-cost error correction scheme is an efficient approach to avoid such a permanent effect. Existing techniques employ error correction codes with considerably high overhead to mitigate MBUs in configuration frames. In this paper, we present a low-cost error-detection code to detect MBUs in configuration frames as well as a generic scrubbing scheme to reconstruct the erroneous configuration frame based on the concept of erasure codes. The proposed scheme does not require any modification to the FPGA architecture. Implementation of the proposed scheme on a Xilinx Virtex-6 FPGA device shows that the proposed scheme can detect 100% of MBUs in the configuration frames with only 3.3% resource occupation, while the recovery time is comparable with the previous schemes.

Multiple bit upsets due to radiation-induced soft errors are a major concern in nanoscale technology nodes. Once such errors occur in the configuration frames of an FPGA device, they permanently affect the functionality of the mapped design. The combination of error correction schemes and configuration scrubbing is an efficient approach to avoid such permanent errors. Existing solutions exploit coding techniques with considerably high overhead to protect configuration frames against multiple bit upsets. In this paper, we propose a generic scrubbing scheme which reconstructs the erroneous configuration frame based on the concept of erasure codes. Our proposed scheme does not require any changes to the FPGA architecture. Experimental results on a Xilinx Virtex-6 FPGA device show that the proposed scheme achieves error recovery coverage of 99.30% with only 3% resource occupation while the mean time to repair is comparable with previous schemes.

Bias Temperature Instability (BTI) plays a significant role in transistor aging. As the device dimensions shrink due to technology scaling, this problem poses serious reliability issues. Field Programmable Gate Arrays (FPGAs) use very advanced nano-scaled CMOS technologies, which makes them vulnerable to BTI-induced aging. Previous studies have analyzed the relationship between the configuration of Look-Up Tables (LUTs) and the input signal probabilities against BTI-induced aging of LUTs. In this paper, we propose two methods to mitigate BTI-induced aging in LUTs. The mitigation is performed by manipulating the configuration of the used LUTs and their input signal probabilities, while maintaining the functionality of the mapped design. We implemented the proposed methods using the academic tool Verilog to Routing (VTR). The experimental results show that our methods can mitigate BTI-induced aging of LUT substantially and improve the lifetime of the FPGA-mapped designs, on average, by more than 200%.