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Routing algorithms were extensively studied first in multi-computer systems, then in multi- and many-core architectures. Among the commonly used routing techniques, the turn model seems the most promising solution when targeting adaptiveness. Based on the turn model, several alternative approaches with different turn prohibition schemes were proposed. This paper gives a new theoretical background for designing deadlock-free partially adaptive logic-based distributed routing algorithms that are based on the turn model. Two properties are presented, including a necessary and sufficient condition to prove that a routing algorithm is deadlock-free as long as turn restrictions follow a modular distribution. Existing approaches can be considered a subset of the solution space identified by this work. Finally, we propose a novel routing algorithm exhibiting encouraging performance improvements over state-of-the-art approaches.

To face the complex communication problems that arise as the number of on-chip components grows up, photonic networks-on-chip (NoCs) have been recently proposed to replace electronic interconnects. However, photonic NoCs lack efficient laser sources, possibly resulting in an inefficient or inoperable architecture. In this article, we introduce a methodology for the design space exploration of optical NoC mapping solutions, which automatically assigns IPs/cores to the network tiles such that the laser power consumption is minimized. The experimental evaluation shows average reductions of 34.7% and 27.3% in the power consumption compared to, respectively, application-oblivious and randomly mapped photonic NoCs, allowing improved energy efficiency.

This paper presents a model for designing partially adaptive logic-based distributed routing algorithms. Unlike the previous methods, the Lattice-based Turn Model associates turn prohibitions with the points of different full-rank integer lattices. Due to the generality of the proposed model, existing approaches can be considered a subset of the solution space identified by this work. Morover, we propose three theorems that are instrumental to the design of lattice-based routing algorithms. In particular, the second theorem gives a necessary and sufficient condition to prove that a lattice-based routing algorithm is deadlock-free as long as the lattice basis meets certain requirements. Based on the proposed model, a novel routing algorithm, called lattice-based routing algorithm (LBRA), is presented. Simulation results exhibit encouraging performance improvements over state-of-the-art approaches when considering real and synthetic benchmarks. For instance, average 71 and 18 percent latency reductions are observed under transpose1 traffic compared to, respectively, Odd-Even and Repetitive Turn Model routing algorithms. Furthermore, LBRA achieves up to 38 and 17 percent performance improvement under real traffic as compared to Odd-Even and Repetitive Turn Model routing algorithms.

Future many-core systems will require energy-efficient, high-throughput and low-latency communication architectures. Silicon Photonics appears today a promising solution towards these goals. The inability of photonics networks to perform inflight buffering and logic computation suggests the use of hybrid photonic-electronic architectures. In order to exploit the full potential of photonics, it is essential to carefully design the path-setup architecture, which is a primary source of performance degradation and power consumption. In this paper, we propose a new path-setup approach which can put allocated circuits in a stand-by state, rapidly restoring them when needed. Path-setup messages are sent using a flooding routing strategy to enhance the possibility of finding free optical paths. We compare the proposed approach with a commonly used path-setup strategy as well as some other alternatives available. The results exhibit encouraging improvements in terms of both performance and energy consumption.

Next-generation chip multiprocessors will require communication performance levels that cannot be achieved by traditional electronic ON-chip interconnects. Silicon photonics has recently emerged as a promising alternative to handle future communication needs thanks to the ultrahigh bandwidth and low power consumption. Optical networks-on-chip (ONoCs) are affected by insertion loss and crosstalk noise effects, which constrain the network scalability and impact the power consumption. This paper proposes a hybrid electronic/photonic, hybrid-topology ONoC (H2ONoC), based on a novel architecture aimed at mitigating the above effects. This paper provides a thorough description of the H2ONoC architectures as well as an experimental evaluation based on both synthetic benchmarks and real-world applications. Compared with hybrid mesh- and torus-based network-on-chip architectures, H2ONoC achieves, respectively, 13% and 18% less insertion loss, 32% and 8% less energy consumption under synthetic traffic, 74% and 14% less energy consumption with real applications, as well as better SNR when the system size scales up.

Multi-Processor System-on-Chip (MPSoC) applications can rely today on a very large spectrum of interconnection architectures determining various trade-offs between cost and performance. An automated methodology for optimizing FPGA-based MPSoC interconnect architectures is summarized in this poster paper. Based on the application communication requirements, the methodology concurrently defines the structure of the interconnect and the communication task scheduling, taking into account possible dependencies between tasks under given area constraints. The resulting architecture improves the level of communication parallelism while containing area and power costs.

Multiprocessor Systems-on-Chip (MPSoC) applications can rely today on a very large spectrum of interconnection topologies potentially meeting given communication requirements, determining various trade-offs between cost and performance. Building interconnects that enable concurrent communication tasks introduces decisive opportunities for reducing the overall communication latency. This work identifies three levels of parallelism at the interconnect level: global parallelism across different independent domains; local or intradomain parallelism, relying on inherently concurrent interconnect components such as crossbars; and interdomain parallelism, where multiple concurrent paths across different local domains are exploited. We propose an automated methodology to search the design space, aimed at maximizing the exploitation of these forms of parallelism. The approach also takes into consideration possible dependencies between communication tasks, which further constrains the design space, making the identification of a feasible solution more challenging. By jointly solving a scheduling and interconnect synthesis problem, the methodology turns the description of the application communication requirements, including data dependencies, into an on-chip synthesizable interconnection structure along with a communication schedule satisfying given area constraints. The article thoroughly describes the formalisms and the methodology used to derive such optimized heterogeneous topologies. It also discusses some case studies emphasizing the impact of the proposed approach and highlighting the essential differences with a few other solutions presented in the technical literature.

This work proposes an automated methodology for optimizing FPGA-based many-core interconnect architectures. Based on the application communication requirements, the methodology concurrently defines the structure of the interconnect and the communication task scheduling, taking into account possible dependencies between tasks under given area constraints. The resulting architecture improves the level of communication parallelism that can be exploited while keeping area costs low. The paper thoroughly describes the proposed approach and discusses a few case-studies showing the impact of the proposed technique.

The choice of the communication topology in many systems is of vital importance because it affects the entire inter-component data traffic and impacts significantly the overall system performance and cost. On the other hand, there is a very large spectrum of interconnection topologies that potentially meet given communication requirements, determining various trade-offs between cost and performance. This work proposes an automated methodology to choose among all of these possibilities, avoiding a manual and time consuming design space search process. The methodology takes as input the description of the application communication requirements, and gives as output an on-chip synthesizable interconnection structure satisfying given area constraints. Targeted at FPGA technologies, the approach generates an interconnection structure combining crossbars and shared buses, connected through bridges, yielding a scalable, efficient structure. To the best of the authors' knowledge, it provides the first method to automatically generate FPGA-based communication architectures where heterogeneous communication elements, such as shared buses and crossbar switches, coexist in a network inherently supporting multiple communication paths. The resulting architecture improves the level of communication parallelism that can be exploited, while keeping area requirements low. The paper thoroughly describes the formalisms and the methodology used to derive such optimized heterogeneous topologies. It also discusses a couple of case-study applications emphasizing the impact of the proposed approach and highlighting the essential differences with a few other solutions in the literature.