The systems used in the automotive field for V2X (vehicle-to-everyone) communication represent one of the main points in the development of the autonomous vehicles. The design of an ECU (Electronic Control Unit) in order to ensure commu-nications between vehicles is achieved by most car companies. The standard used in the development of this ECU is AUTOSAR (Automotive Open System Architecture). This paper presents how an implemented V2V / V2I system (vehicle-to-vehicle / vehicle-to-infrastructure) is converted to the AUTOSAR architecture. It contains the presentation of the methods of development and implementation of the system on the vehicles, regardless of their age. The proposed V2V / V2I communication system called CommA_v.x (Communication Auto-motive x version) is a system that communicates with the main ECU of the vehicle, distance sensors located on the vehicle, road infrastructure, vehicles around the car but also with the owner / driver. Also, this paper presents the hardware and software differ-ences between the versions of this system, including the simulation of functionality in road traffic.

The purpose of this research article is to create an optimized purpose for the Dijkstra algorithm, with a superior degree of efficiency. This research proposes also, in the first instance, an innovative and efficient analysis of the Dijkstra's and Roy-Floyd algorithms. This proposed method is useful in various application cases, such as information grouping systems associated with a graph with a small but high node density. The analysis part explains the strategies chosen for today's parallel solutions and comparisons with the implemented method. It can be stated that the parallelization solution proposed in the article is specific to a configuration. There will be also presented other strategies considering the grouping systems for the tests with many nodes and edges. The algorithm for determining the shortest path is presented and tested at the multi-language level in different contexts and scenarios.

A bit heap is a data structure that holds the unevaluated sum of an arbitrary number of bits, each weighted by some power of two. Most advanced arithmetic cores can be viewed as involving one or several bit heaps. We claim here that this point of view leads to better global optimization at the algebraic level, at the circuit level, and in terms of software engineering. To demonstrate it, a generic software framework is introduced for the definition and optimization of bit heaps. This framework, targeting DSP-enabled FPGAs, is developed within the open-source FloPoCo arithmetic core generator. Its versatility is demonstrated on several examples: multipliers, complex multipliers, polynomials, and discrete cosine transform.