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Xuan Thuy Ngo

dblp:136/4513 · DBLP profile ↗
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6ranked-venue papers
3as first author
0since 2021 · last 2020
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 4 · 3 first-authorSecurity and privacy · 2Software engineering, systems software and programming languages · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Network and information security
2 papers
Hardware security and side channels · 90% Cryptographic primitives and cryptanalysis · 10%
Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 62% Integrated circuit design · 38%

Topics — the 7 heaviest of 7, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Hardware security and side channels › physical attacks
probing attack
0.312017
Cryptographically Secure Shield for Security IPs Protection · IEEE Trans. Computers 2017
Hardware security and side channels
side-channel attack
0.312017
Cryptographically Secure Shield for Security IPs Protection · IEEE Trans. Computers 2017
Hardware security and side channels
fault attack countermeasure
0.212016
PLL to the rescue: a novel EM fault countermeasure · DAC 2016
Electronic design automation
design flow
0.212016
PLL to the rescue: a novel EM fault countermeasure · DAC 2016
Cryptographic primitives and cryptanalysis
block cipher
0.112017
Cryptographically Secure Shield for Security IPs Protection · IEEE Trans. Computers 2017
Integrated circuit design › analog and mixed-signal circuits
mixed-signal circuit design
0.112016
PLL to the rescue: a novel EM fault countermeasure · DAC 2016
Integrated circuit design › analog and mixed-signal circuits › mixed-signal circuit design
phase-locked loop
0.112016
PLL to the rescue: a novel EM fault countermeasure · DAC 2016

Methods — techniques the papers use, named apart from their topics

PLL-based sensor · 0.5
YearPublicationVenuePosition
2020 Machine Learning Based Hardware Trojan Detection Using Electromagnetic Emanation
Junko Takahashi, Keiichi Okabe, Hiroki Itoh, Xuan Thuy Ngo, Sylvain Guilley, Ritu Ranjan Shrivastwa, Mushir Ahmed, Patrick Lejoly
ICICS4
2017 Cryptographically Secure Shield for Security IPs Protection
abstract
Probing attacks are serious threats on integrated circuits. Security products often include a protective layer called shield that acts like a digital fence. In this article, we demonstrate a new shield structure that is cryptographically secure. This shield is based on the lightweight block cipher and independent mesh lines to ensure the security against probing attacks of the hardware located behind the shield. Such structure can be proven secure against state-of-the-art invasive attacks. Then, we evaluate the impact of active shield on the performance of security IPs as PUF, TRNG, secure clock and AES using a set of fabricated ASICs with 65 nm CMOS technology of STMicroelectronics. Also, the impact of active shield on Side-Channel Attack (SCA) is evaluated.
Xuan Thuy Ngo, Jean-Luc Danger, Sylvain Guilley, Tarik Graba, Yves Mathieu, Zakaria Najm, Shivam Bhasin
IEEE Trans. Computers1
2016 PLL to the rescue: a novel EM fault countermeasure
abstract
Electromagnetic injection (EMI) is a powerful and precise technique for fault injection in modern ICs. This intentional fault can be utilized to steal secret information hidden inside of ICs. Unlike laser fault injection, tedious package decapsulation is not needed for EMI, which reduces an attacker's cost and thus causes a serious information security threat. In this paper, a PLL-based sensor circuit is proposed to detect EMI reactively on chip. A fully automatic design flow is devised to integrate the proposed sensor together with a cryptographic processor. A high fault detection coverage and a small hardware overhead are demonstrated experimentally on an FPGA platform.
Noriyuki Miura, Zakaria Najm, Wei He 0015, Shivam Bhasin, Xuan Thuy Ngo, Makoto Nagata, Jean-Luc Danger
DAC5
2015 Hardware trojan detection by delay and electromagnetic measurements
Xuan Thuy Ngo, Ingrid Exurville, Shivam Bhasin, Jean-Luc Danger, Sylvain Guilley, Zakaria Najm, Jean-Baptiste Rigaud, Bruno Robisson
DATE1
2015 Integrated Sensor: A Backdoor for Hardware Trojan Insertions?
abstract
Embedded system face a serious threat from physical attacks when applied in critical applications. Therefore, modern systems have several integrated sensors to detect potential threats. In this paper, we put forward a new issue where these sensors can open other security loopholes. We demonstrate that sensors, which are deployed to prevent faults, can be exploited to insert effective and almost zero-overhead hardware Trojans. Two case studies are presented on Xilinx Virtex-5 FPGA. The first case study exploits the in-build temperature sensor of Virtex-5 system monitors while the other exploits a user deployed sensor. Both the sensor can be used to trigger a powerful Trojan with minimal and at times zero overhead.
Xuan Thuy Ngo, Zakaria Najm, Shivam Bhasin, Debapriya Basu Roy, Jean-Luc Danger, Sylvain Guilley
DSD1
2013 Hardware Trojan Horses in Cryptographic IP Cores
abstract
Detecting hardware trojans is a difficult task in general. In this article we study hardware trojan horses insertion and detection in cryptographic intellectual property (IP) blocks. The context is that of a fabless design house that sells IP blocks as GDSII hard macros, and wants to check that final products have not been infected by trojans during the foundry stage. First, we show the efficiency of a medium cost hardware trojans detection method if the placement or the routing have been redone by the foundry. It consists in the comparison between optical microscopic pictures of the silicon product and the original view from a GDSII layout database reader. Second, we analyze the ability of an attacker to introduce a hardware trojan horse without changing neither the placement nor the routing of the cryptographic IP logic. On the example of an AES engine, we show that if the placement density is beyond 80%, the insertion is basically impossible. Therefore, this settles a simple design guidance to avoid trojan horses insertion in cryptographic IP blocks: have the design be compact enough, so that any functionally discreet trojan necessarily requires a complete replace and re-route, which is detected by mere optical imaging (and not complete chip reverse-engineering).
Shivam Bhasin, Jean-Luc Danger, Sylvain Guilley, Xuan Thuy Ngo, Laurent Sauvage
FDTC4