Synthesis tools can unlock the potential of analog architectures to achieve real-time computation, signal processing, inference and learning for low$S$WaP systems in commercial timescales. We present a methodology and results towards system analog and mixed-signal synthesis both for FPAAs and Custom Analog IC design. Building on previously efforts on large-scale Field Programmable Analog Arrays (FPAA) targeting tools enables tools capable of synthesizing new ICs. The IC synthesis is built upon our recent work on analog & mixed-signal programmable CMOS standard cell library that can be used across a range of CMOS process nodes (e.g. 180nm, 130nm, 65nm, 28nm, and 16nm CMOS). The entire tool-flow is being developed as an open-source tool that can be widely available. These approaches enable moving analog and mixed-signal design towards structured Design Space Exploration (DSE).

This effort describes a Python-based open-source tool to synthesize a mixed-signal reconfigurable IC fabric, known as large-scale Field Programmable Analog Array (FPAA) fabric. This tool starts from a high-level definition for an FPAA fabric to lower into gathered islands for each Computational Analog Blocks (CAB) and Computational Logic Blocks (CLB), and then extends the Ashes tool to first place and route each different island, and then place and route the full fabric. This tool integrates with the Ashes tool and expands both tools to enable synthesis of a configurable analog or mixed-signal reconfigurable fabric with other analog & mixed-signal standard cell components. The fabricated fabric could be targeted through the Ashes tool that integrates VPR into its place and route flow. The synthesis builds from recent innovations of programmable analog & mixed-signal standard cells that utilize Floating- Gate (FG) elements for their high-precision parameters. This effort demonstrates this synthesis entirely for 350nm standard cells with configurable chips that are synthesized to tapeout. These techniques generalize to other analog standard cell libraries (e.g. 130nm, 65nm, 16nm). A recent critical effort is the development of programmable analog & mixed-signal standard cells that utilize Floating-Gate (FG) elements for their high-precision parameters. These concepts, in-turn, enable the opportunity to both abstract higher levels of analog computation and enable large-scale analog synthesis.

Analog Hopfield networks perform continuous energy minimization, leading to efficient and near-optimal solutions to nonpolynomial (NP)-hard problems. However, practical implementations suffer from scaling and connectivity issues. A programmable and reconfigurable analog Hopfield network is presented that addresses these challenges through a reconfigurable Manhattan architecture with a high-precision 14-bit floating-gate (FG) compute-in-memory (CiM) fabric. The network is implemented on a field programmable analog array (FPAA) and experimentally tested on three different NP-hard problems with different scaling challenges: Weighted Max-Cut (high connectivity and weight precision), traveling salesman problem (TSP) (high connectivity and medium weight precision), and Boolean Satisfiability/3SAT (low connectivity and weight precision) where it solved each problem optimally in microseconds.

This work presents an experimentally measured, implemented, openly-available programmable analog standard cell library in Skywater’s 130nm CMOS process. Programmability enables standard-cell components, eliminating the need for large number of device geometries required in classic analog design. This effort presents the methodology in developing these analog standard cell library and integrating synthesis with these cells.

Physical computing techniques can efficiently solve combinatorial optimization problems and could outperform conventional digital techniques. This paper presents the first direct comparison of two physical quadratic optimization solvers: analog Hopfield and Ising networks. Both networks are built in a large scale Field Programmable Analog Array (FPAA) and two NP-hard problems (max-cut and associative memory) are solved over various initial conditions and graphs. The convergence time, energy, power, and peripheral circuitry of the two networks is then compared where it is found that the Hopfield network outperforms the Ising networks in these test cases.

This effort develops the first rich suite of analog and mixed-signal benchmark of various sizes and domains, intended for use with contemporary analog and mixed-signal designs and synthesis tools. Benchmarking enables analog-digital co-design exploration as well as extensive evaluation of analog synthesis tools and the generated analog/mixed-signal circuit or device. The goals of this effort are defining analog computation system benchmarks, developing the required concepts for higher-level analog and mixed-signal tools to utilize these benchmarks, and enabling future automated architectural design space exploration (DSE) to determine the best configurable architecture (e.g., a new FPAA) for a certain family of applications. The benchmarks comprise multiple levels of an acoustic , a vision , a communications , and an analog filter system that must be simultaneously satisfied for a complete system.

Integrated circuit (IC) design for analog computing requires similar toolflows and synthesis as large-scale digital systems, in-turn necessitating a library of general-purpose analog cells. To this end, we present a programmable, floating-gate (FG)-based analog standard cell library in a commercially available 65 nm process that allows analog IC designers to use synthesis tools with an abstracted design mindset similar to large-scale digital design. We fabricate the test cells, which include filters with programmable corners, an analog classifier, and an arbitrary waveform generator (AWG); experimentally characterize FG programming; and experimentally demonstrate the performance of the standard cells. Overall, the standard cells achieve a similar or smaller footprint than previous approaches while leveraging the benefits of FG programming at smaller technology nodes.

This paper discusses physical computing for solving optimization problems using a Hopfield network built on a Field Programmable Analog Array (FPAA). A core Hopfield circuit is presented that uses a programmable Vector-Matrix-Multiply (VMM) and Transconductance Amplifier (TA). The circuit dynamics of the VMM and effects of mismatch are discussed. The analog Hopfield network is evaluated by inputting a graph to the network and solving the NP-hard max-cut problem. Experimental results show convergence time in the order of microseconds towards a optimal solution on a four and ten node graph.

This effort shows the design, measurement, and characterization of a BandPass Filter (BPF) with similar Q adaptation properties seen in the nonlinear dynamics of the basilar membrane in the mammalian cochlea. Starting from low-pass Hopf bifurcations using programmable on-chip Transconductance Amplifiers (TA), a BPF is demonstrated that enables Q adaptation from 25–30 to 1 in roughly 1000 change in amplitude, resulting in a near instantaneous gain adaptation and higher dynamic range. Where the dynamic range of typical BPF banks is limited to the SNR of the individual filter, the adaptive BPF through a Hopf bifurcation enables high dynamic range even with moderate SNR at a given signal level, demonstrated on a large-scale Field Programmable Analog Array (FPAA). This block becomes the basis for higher dynamic range BPFs.

We present a project-based alternative to a classical senior-level first Analog IC design course. This hands-on approach is enabled through a systematic approach to on-line lectures and course material, as well as open-source IC design process (Skywater 130nm CMOS) and tools (magic, Xschem) that are capable of fabricating working ICs. This realistic student design experience builds student confidence in designing 10-100 transistor circuits that could be fabricated on this IC process.

The growth of large-scale analog and mixed-signal configurable computing systems, requires addressing analog and mixed-signal test questions similar to the development of digital IC testing over the past three decades that includes numerous on-chip self-testing mechanisms. End-to-end configurable computing systems require verification using an input sensor or the emulation of an input sensor device and measuring the resulting refined digital, or near digital, output. Verifying and calibrating these configurable systems requires a framework for implementing an application in a once-programmed production devices and general procedure for verifying reconfigurable prototype devices.

This effort discusses a programmable Hopf bifurcation element based on Transconductance Amplifiers (TA) that can be directly implemented in configurable hardware (e.g. an SoC FPAA). The TA Hopf bifurcation circuit shows the complete dynamics of a Van der Pol circuit, a Hopf bifurcation prototype. This Low-Pass Filter (LPF) TA-implemented ODE shows the necessary linear dynamics, as well as stable and oscillatory nonlinear dynamics expected near a Hopf bifurcation. This component directly uses the dynamics of the TA devices not translating equations, reducing the implementation complexity.

This paper addresses and experimentally demonstrates a programmable linear equation solver by analog computation. A set of differential equations using transconductance devices directly translated from circuit theory converges to the linear equation solution. These energy-efficient analog techniques are experimentally demonstrated in a configurable analog platform. The resulting analog linear equation solution circuits are effectively analog filters. The paper analyzes the algorithmic issues and analog numerical analysis issues, including accuracy, convergence time, and the interpretation of condition number for analog solutions.

This work demonstrates a Continuous-Time (CT) Ladder filter using transconductance amplifiers as an approximate delay stage implemented on a large-scale Field Programmable Analog Array (FPAA) and characterized on an SoC FPAA. We experimentally demonstrate a reprogrammable CT Analog linear-phase filter by utilizing the ladder filter delay element and Vector-Matrix Multiplication (VMM) both compiled on the SoC FPAA. Using the Ladder Filter as a programmable CT delay operation enables a traditionally difficult analog signal operation. This effort extensively models and characterizes the ladder filter delay stage in terms of its transfer function, delay tunability, power requirements, distortion, and SNR. The theoretical development is compared to experimental measurements on an SoC FPAA with programmable ladder filter delay of 2.9μs and 4.2μs for multiple input frequencies (e.g. 5kHz, 20kHz). In addition, we show that VMMs can compensate the non-idealities found in the ladder filter delay-line operation.

This work presents a mixed-signal cell library built through multiple generations of educational experiences. Digital standard cell libraries are ubiquitous for commercial and academic IC design. Analog standard cell libraries are rare within system-level analog design. Educational efforts in analog system design provide a path for developing these standard cell libraries. The effort included determining the essential blocks for this standard cell library based on previous explorations, as well as constraints to make the layout efficient. Analog and mixed-signal standard cells enable compilation of a high-level description of analog and mixed signal designs to full IC layout. A standard cell library definition allows components designed in any process to have broad utilization. A high-level to layout compilation empowers rapid movement between different IC processes.

Even though analog computation is better suited for differential equation solutions (ODE, PDE), sometimes it needs to solve systems of linear equations. This discussion focuses on analog solutions of linear equation systems, implemented on a configurable platform. Digital systems rely on solving linear equations as the fundamental numerical computation. Systems of linear equations are used to solve static circuits illustrating that at least a reduced class of analog physical linear system computation should be possible. The analog approaches utilize iterative techniques, setting up a set of ODEs to solve the system of linear equations, rather than relying on matrix decompositions (e.g. LU decomposition). The approach allows for multiple potential configurable circuit approaches. A set of amplifier networks has been designed to demonstrate the solutions for different matrices. These techniques provide energy-efficient continuous-time solutions. The resulting algorithm has been studied considering the analog numerical analysis for the solution and convergence time.

An analog Vector Matrix Multiplier (VMM) along with its interface through Multi-Input Translinear Elements (MITE) is compiled on a reconfigurable Field Programmable Analog Array (FPAA) on a 350nm process. The paper focuses on the tuning algorithm to set the weights on the VMM as well as to produce levels of voltage near the power supply rails, Vdd, to the source-driven VMMs, by application of a wide range of input levels. The constraints during the design and implementation process, accounting for the mismatch in devices, are discussed. A significant reduction in the variation in the levels of the desired voltage has been demonstrated in the paper.

Large-scale field-programmable analog array (FPAA) devices could enable ubiquitous analog or mixed-signal low-power sensor to processing devices similar to the ubiquitous implementation of the existing field-programmable gate array (FPGA) devices. Design tools enable high-level synthesis to gate/transistor design targeting today's FPGA devices and the opportunity for analog or mixed-signal applications with FPAA devices. This discussion will illustrate the FPAA concepts and FPAA history. The development of FPAAs enables the development of multiple potential metrics, and these metrics illustrate future FPAA device directions. The system-on-chip (SoC) FPAA devices illustrate the IC capabilities, computation, tools, and resulting hardware infrastructure. SoC FPAA device generation has enabled analog computing with levels of abstraction for application design.

The neuronal responses through excitatory and inhibitory synapses are implemented on a reconfigurable and programmable platform. The synaptic cleft between the pre synaptic and post synaptic neuron has been depicted as a ramp generator while the post synaptic potentials are observed from the transistor channel neuron model which emulates the ion channels in biological neurons. The synaptic strengths are tuned by modulating the charge on the floating gate devices on the hardware demonstrated through particular voltage levels and time constants. The models have been designed and built in such a way that the tools associated with the chip make it possible to build up and compile a bigger network of neurons and synapses. The experimental measurements are taken from the circuits compiled on a Field Programmable Analog Array fabricated on a 350nm process.

This paper discusses the first step in analog (and mixed signal) abstraction utilized in large-scale Field Programmable Analog Arrays (FPAA), encoded in open-source SciLab/Xcos based toolset. Analog computation becomes relevant with the advent of FPAA devices, particularly the SoC FPAA devices and resulting design tools. Analog and digital systems have tools to model resolution and computational noise and computation energy; analog and digital approaches have their own optimal computing regions. Abstraction of Blocks in the FPAA block library makes the SoC FPAA ecosystem accessible to system-level designers while still enabling circuit designers the freedom to build at a low level. The FPAA block library provides a starting point for discussing the fundamental block concepts of analog computational approaches. These discussions begin the framework for a theory of analog algorithm complexity theory, and careful methods for comparison of techniques.

This paper is grounded in the experiences of our Fall 2016 full FPAA implementation in a junior level class Georgia Tech. This paper focuses on discussing the circuit design implications learned when teaching with a highly configurable IC (SoC FPAA), as well as implications for circuit education. Three questions are addressed in turn: subthreshold and near-threshold MOSFET design as a foundational circuit concept, moving past design of op-amps as a central IC design teaching focus, and programmable transconductance-capacitance filters as fundamental filter approach. Configurable hardware (FPAA) creates a unique position enabling these next directions in circuits and educational applications.

This paper presents an embedded learning algorithm, a one-layer VMM + WTA classifier, on a Large-Scale Field Programmable Analog Array (FPAA), The technique enables opportunities for embedded, ultra-low power machine learning, techniques typically considered for large servers. A VMM + WTA single, one-layer network is a universal approximator. An on-chip learning algorithm was developed to train this physical classifier. A clustering step determines the initial weight set for ideal target and background values. Null symbols are important for the algorithm and are set from midpoints of the target values. Experimental measurements are shown for this learning classifier implemented on an SoC FPAA device.

The spiking dynamics from a Hodgkin Huxley neuron, implemented on a reconfigurable and programmable platform is presented here. The similarity between biology and silicon has been exploited to model the ion channels in the neuron, and their voltages and time constants on hardware. We demonstrate the reproducibility of the results by replicating the dynamics across different chips along with a discussion on the methodology of tuning to reproduce similar responses. The reconfigurability enables one to make use of a single primary design to obtain a variety of results. The measurements are taken from the system compiled on a Field Programmable Analog Array (FPAA) fabricated on a 350nm process.

This brief investigates temperature compensation techniques for circuits and systems on a reconfigurable platform. The work demonstrates use of large-scale reconfigurable system-on-chip for reducing the variability of circuits and systems compiled on a floating gate (FG)-based field-programmable analog array (FPAA). The work presents current and voltage reference which could help in reducing the variability caused due to changes in temperature. These references are standard blocks in the Scilab/Xcos environment, which could be easily compiled on the FPAA. An FG-based current reference is then used for biasing a second-order $G_{m}-C$ bandpass filter to demonstrate the compilation and usage of these voltage/current reference in a reconfigurable fabric. The large-scale FG FPAA presented here is fabricated in 350-nm CMOS process.

We present a calibration flow for a large-scale Floating-Gate (FG) System-on-Chip (SoC) Field Programmable Analog Array (FPAA) to enable analog system design and built-in self test. We focus on calibration of the FG programming infrastructure, Digital-Analog Converters (DAC) and Analog-Digital Converters (ADC), as well as characterization of hot-electron injection parameters. This paper shows the results of a compiled Winner-Take-All (WTA) circuit on three different calibrated chips.

An openly available simulator is presented here, which can be used to design, characterize and simulate circuits including floating gate (FG) components and larger systems building upon these elements, while measuring the silicon data too from the Field Programmable Analog Array (FPAA), incorporated within the same tool infrastructure. A single system for simulation as well as obtaining experimental measurements from reconfigurable hardware is significantly useful especially in classroom environments. The efficiency of our simulator is shown through the comparison in performance to that of conventional simulators and its close overlap with the data measured for the same experiments from the FPAA fabricated in a 350nm process.

This paper presents a low-power speech detector on a fully reconfigurable Field Programmable Analog Array (FPAA). The entire system is designed and compiled on a FPAA fabricated in 0.35μm CMOS process. The system uses 12 parallel bank of band-pass filters to extract features. The outputs of the filter bank are used by a single layer of 12×2 Vector Matrix Multiplication (VMM) and Winner Take All (WTA). The weights are stored on the VMM using pFET floating gate transistor. The power consumption of the analog system is 155.6μW with a 2.5 V power supply. The low power consumption allows the use of such a system for portable and remote sensing applications. Further, the paper investigates the performance of the system by adding white gaussian noise to the input signal. The system has an accuracy of 99.94% when the input has a SNR of 20dB and of 74% with a SNR of 8dB.

This paper presents path planning using reconfigurable analog very large scale integrated (AVLSI) circuits. Existing research has shown that custom AVLSI circuits known as application specific integrated circuits (ASICs) can theoretically be used for path planning. There are two main drawbacks to using custom ASICs: 1) circuit designs are fixed to some extent (not changeable) and 2) long design cycle/fabrication time (order of months). Reconfigurable analog circuits called field-programmable analog arrays (FPAAs) have been used to implement a variety of AVLSI circuits in a short time (order of minutes). This paper presents an algorithm for mapping a robot's environment onto an FPAA, and then presents hardware results using an FPAA to implement the path-planning algorithm. Experimental results and analysis are presented for 24 environment scenarios. Digital search methods like breadth-first search have solutions which scale on the order of O(4d) whereas this paper will show our analog solution is on the order of O(d) where d is the depth of the solution.

We present a calibration flow for a large-scale floating-gate (FG) system-on-chip field programmable analog array. We focus on characterizing the FG programming infrastructure and hot-electron injection parameters, MOSFET parameters using the EKV model, and calibrating digital-analog converters and analog-digital converters. In addition, threshold voltage mismatches on FG devices due to their indirect structure are characterized using on-chip measurement techniques. The calibration results in enabling a digital approach, where a design can be programmed without having to deal with the local and global mismatches, on a reconfigurable analog system. This paper shows the results of a compiled nonlinear classifier block comprising a vector-matrix-multiplier and a winner-takes-all on three different calibrated chips.

This paper presents the assessment results of using Field Programmable Analog Arrays (FPAAs) and its concomitant design automation software, RASP Tools, in an analog graduate level course to integrate hands-on activities for learning. We describe our teaching methodology as well as experiments involving the FPAA SoC and its tool suite created for this course. We are evaluating the student satisfaction of using RASP Tools and FPAA SoCs for analog design and our blended approach to convey this material. Metrics considered are students' perception of hardware & software capabilities, self-efficacy in the core areas, and their assessment of the course methodology.

This document describes the live demonstration of FPAA Demonstration Controlled through Android-Based Device1. This demonstration requires no additional resources other than the basic resources (power plug, a table and pin wall) to be provided to each demonstration 2. The demonstration will use a Google Nexus 7 tablet and a RASP 3.0 board (most likely multiple boards), which the authors will transport. The demonstration application to interface with the board runs on the tablet, as well as laptops, to show the relevant design tools to interested users. This application could be downloaded to individual devices (our long term plan), although it is harder to predict if these options will be ready during the demonstration.

The drain current of a transistor in subthreshold operation exhibits a temperature dependence due to the thermal voltage, kT/q. The magnitude of this temperature dependence, as measured in 1979, was reported to be greater than the expected kT/q due to increased interface state densities; however, thirty years later, we saw little dependence. This behavior is of interest because subthreshold-enabled asynchronous circuits allow for operation below threshold with optimal power performance at threshold, but the original work suggests that static current will increase with temperature at a rate greater than predicted by the thermal voltage alone. Furthermore, the previously recorded behavior was very similar to what would be expected from ESD diodes. We revisit the work by Card et al., and present data from a commercially available 350nm process over temperature.

This demonstration presents live hands-on experience of the System on Chip (SoC) large-scale Field Programmable Analog Array (FPAA) IC [1] through a complete PC Board and high-level tool interface [2]. Figure 1a shows the demonstration requires only basic power connection to the laptop. The hardware includes an FPAA demonstration board and a Digilent USB device to enable a scope / function generator functionality.

We present a novel remote test system, enabled by configurable analog-digital ICs to create a simple interface for a wide range of experiments, whether in research or educational directions. Our remote test system utilizes a nearly identical setup to the existing large-scale Field Programmable Analog Array (FPAA) toolset; a mixed-mode configurable system with a common digital interface (e.g. USB) enables a nearly seamless transition. The system overhead requirements are straightforward, requiring simple email handling, available over almost all network systems with no additional requirements. We present using the FPAA devices and baseline tool framework, present overview examples for the remote system.

Figure 1 illustrates part of the user experience of the remote test system for this demonstration. This demonstration requires only basic resources (power plug and table), utilizing a wireless network as available. Participants can experience both sides of the remote system, one laptop running the remote system and infrastructure, and a second laptop (or more) only running the resulting tools and taking experimental data. Participants can try different circuits among many options already available for the user to use or modify.

We present a survey and analysis of processor power efficiency, showing results from the first personal computer until the present day that analyzes the metric of multiply- accumulate (MAC) energy per operation. MAC performance is critical for continued scaling of signal processing applications. We derive our results from published work and published CPU databases, and we hypothesize that a Powerwall exists, above which we do not predict Moore's law will bring the current digital computing paradigm. Our results show that this Powerwall exists in a band from 10 to 30 GMAC/W.

This paper presents a floating-gate (FG)-based, field-programmable analog array (FPAA) system-on-chip (SoC) that integrates analog and digital programmable and configurable blocks with a 16-bit open-source MSP430 microprocessor (μP) and resulting interface circuitry. We show the FPAA SoC architecture, experimental results from a range of circuits compiled into this architecture, and system measurements. A compiled analog acoustic command-word classifier on the FPAA SoC requires 23 μW to experimentally recognize the word dark in a TIMIT database phrase. This paper jointly optimizes high parameter density (number of programmable elements/area/process normalized), as well as high accessibility of the computations due to its data flow handling; the SoC FPAA is 600 000 × higher density than other non-FG approaches.

We present the first integrated system to handle heterogeneously used and programmed floating-gate (FG) elements in a single modular approach. We focus on IC design, integration, characterization, and algorithmic development of an integrated FG programming system for a large-scale field-programmable analog array. We work through tunneling approaches to initialize the FG devices for precision programming, as well as hot-electron injection approaches for precise device programming.

We show a Field-Programmable Analog Array complemented with post-processed memristors (FPAA/memristor hybrid circuit), and present it as a platform for analog signal processing. The FPAA is fabricated on CMOS and uses floating-gate transistors (FGT) to realize programmable wiring fabrics and analog computing resources. The memristors, post-processed on top of the FPAA, are analog, which means that their conductance can be programmed in a continuous fashion. We highlight the key differences between FGTs and memristors, and discuss how analog signal processing tasks could be divided between them. Experimental results of the FPAA-memristor hybrid circuit are presented.

This paper presents a floating gate Ion Sensitive Field Effect Transistor (ISFET) to monitor the activity of breast cancer cells. We use an ISFET to monitor the change in pH of the cell culture media and to observe the apoptosis of the breast cancer cells when treated with staurosporine. Since ISFETs suffer from inherent mismatch and drift in the threshold voltage, predominantly caused due to accumulation of ions on the surface of the gate, we have integrated a floating gate ISFET to calibrate the device. Floating gate ISFETs have been used to program the threshold voltage of the device either by hot electron injection, Fowler-Nordheim tunneling, and UV to remove charges. In this work we use hot electron injection to precisely program the device and tunneling as a global erase. This enables us to precisely record the changes in pH. These floating gate devices have been fabricated in 0.5 µm CMOS process.

Sparse approximation is a hypothesized coding strategy where a population of sensory neurons (e.g. V1) encodes a stimulus using as few active neurons as possible. We present the Spiking LCA (locally competitive algorithm), a rate encoded Spiking Neural Network (SNN) of integrate and fire neurons that calculate sparse approximations. The Spiking LCA is designed to be equivalent to the nonspiking LCA, an analog dynamical system that converges on a ℓ(1)-norm sparse approximations exponentially. We show that the firing rate of the Spiking LCA converges on the same solution as the analog LCA, with an error inversely proportional to the sampling time. We simulate in NEURON a network of 128 neuron pairs that encode 8 × 8 pixel image patches, demonstrating that the network converges to nearly optimal encodings within 20 ms of biological time. We also show that when using more biophysically realistic parameters in the neurons, the gain function encourages additional ℓ(0)-norm sparsity in the encoding, relative both to ideal neurons and digital solvers.

We present a large-scale field programmable analog array that enables floating-gate (FG) adaptive circuits using FG-based switch technology. We present a novel architecture technology that enables switch routing with FG elements for signals resulting from high voltage adapting FG elements. We present careful analysis and characterization of the FG structure, including programming ranges, electron tunneling paths, to show the indirect programming structure involving an nFET device can handle the signals. We present the experimental data (350-nm commercial CMOS process) for a single-transistor adaptive structure, for a compiled autozeroing amplifier, and for multiple adaptive FG circuits.

This paper presents hardware results for a neuromorphic approach to path planning using a neuron array integrated circuit. The algorithm is explained and experimental results are presented showing 100% correct and optimal performance for a large number of randomized maze environment scenarios. Based on neuron signal propagation speed, neuron integrated circuit (IC) path planning may offer a computational advantage over state-of-the-art wavefront planners implemented on field-programmable gate arrays (FPGAs). Analytical time and space complexity metrics are developed in this paper for a neuron ICs planner, and these are verified against experimental data. Optimality and completeness are also addressed. The neuron structure allows one to develop sophisticated graphs with varied edge weights between nodes of the grid. Two interesting cases are presented. First, asymmetric edge costs are assigned to describe cases, which have a certain cost to travel a path in one direction, but a different cost to travel the same path but in the opposite direction. The application of this feature can translate to real world problems involving hills, traffic patterns, and so forth. Second, cases are presented where the nodes near an obstacle are given higher costs to visit these nodes. This is in an effort to keep the autonomous agent at a safe distance from obstacles. This grid weighting can also be used to differentiate among terrains such as sand, ice, gravel, or smooth pavement. Experimental results are presented for both cases.

We describe architectures for audio classification front ends on a reconfigurable analog platform. Real-time implementation of audio processing algorithms involving discrete-time signals tend to be power-intensive. We present an alternate continuous-time system implementation of a noise-suppression algorithm on our reconfigurable chip, while detailing the design considerations. We also describe a framework that enables future implementations of other speech processing algorithms, classifier front ends, and hearing aids.

The vector-matrix multiply and winner-take-all structure is presented as a general-purpose, low-power, compact, programmable classifier architecture that is capable of greater computation than a one-layer neural network, and equivalent to a two-layer perceptron. The classifier generates event outputs and is suitable for integration with event-driven systems. The main sources of mismatch, temperature dependence, and methods for compensation are discussed. We present measured data from simple linear and nonlinear classifier structures on a 0.35-μm chip and analyze the power and computing efficiency for scaled structures.

Large-scale field-programmable analog array ICs have made analog and analog-digital signal processing techniques accessible to a much wider community. Given this opportunity, we present a framework for considering analog signal processing (ASP) techniques for low-power systems. The core of this paper is the definition of an analog abstraction methodology and the creation of a library of high-level analog computation blocks. By abstracting the analog design, we ensure that users have a similar experience to what they would expect with digital design, thus empowering system-level engineers to take advantage of ASP concepts. The result of this paper is to pull analog computation toward system-level development, comparable with the trend in digital system design over the last 30 years.

We present the VMM+WTA structure as a general-purpose, low-power, compact, programmable classifier architecture and demonstrate its equivalence to a 2-layer perceptron. The classifier generates event outputs and is suitable for integration with event-driven systems. We present measured data from simple linear and non-linear classifier structures on a 0.35μm chip and demonstrate the implementation of an XOR function using a 1-layer VMM+WTA classifier.