Demo Data from VLDB 2026 / reviewers in the wild / expert
Predrag Teodorovic
dblp:137/3548
· DBLP profile ↗
2ranked-venue papers
1as first author
1since 2021 · last 2025
0000-0003-1422-4745ORCID · corroborated
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2 · 1 first-author · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Electronic design automation · 91% Emerging computing paradigms · 9% |
Topics — the 4 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation › logic synthesis › logic minimization
boolean function minimization |
0.2 | 1 | 2013 | Recursive Boolean Formula Minimization Algorithms for Implication Logic · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2013 |
Electronic design automation › logic synthesis › switching theory
implication logic |
0.2 | 1 | 2013 | Recursive Boolean Formula Minimization Algorithms for Implication Logic · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2013 |
Electronic design automation
logic synthesis |
0.2 | 1 | 2013 | Recursive Boolean Formula Minimization Algorithms for Implication Logic · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2013 |
Emerging computing paradigms
memristive computing |
0.0 | 1 | 2013 | Recursive Boolean Formula Minimization Algorithms for Implication Logic · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2013 |
Methods — techniques the papers use, named apart from their topics
recursive boolean formula minimization · 0.2
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2025 | Upscale Layer Acceleration on Existing AI HardwareabstractUpscaling layers are important components of modern deep learning networks but often pose computational challenges for hardware (HW) accelerators. This article addresses this issue by introducing a novel layer-replacement technique to efficiently process upscaling layers using existing hardware-supported operations like depthwise convolutions and maximum pooling. To minimize the number of replacement layers, we propose an efficient layer number reduction algorithm. Experimental results on four deep neural networks demonstrate a significant speedup ranging from$1.58\times $to$32.88\times $compared to the original HW/software (SW) execution approach, and from$3.65\times $to$19.21\times $compared to the software-only solution, with minimal hardware overhead (0.068% more field-programmable gate array (FPGA) look-up tables (LUTs)). Notably, our technique introduces no numerical errors and maintains comparable input data processing quality to the original network. Vuk Vranjkovic, Predrag Teodorovic, Rastislav J. R. Struharik |
IEEE Trans. Very Large Scale Integr. Syst. | 2 |
| 2013 | Recursive Boolean Formula Minimization Algorithms for Implication LogicabstractIn this paper are given two novel algorithms for minimization of recursive Boolean formula (RBF), which is adequate for implementation of N-input 1-output Boolean functions (BFs) over basis {imply, false} using two memristors. Both of our algorithms are direct consequence of necessary and sufficient conditions related to regular ordering of positive product terms within recursive formula. The results demonstrate how developed algorithms provide up to 26% gain in average number of implications and shorter recursive Boolean formula length in up to 77% of problem instances than previously published algorithms, tested on the set of all 4-input 1-output BFs. Predrag Teodorovic, Stanisa Dautovic, Veljko Malbasa |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 1 |