VLDB 2026 Research / reviewers in the wild / expert
Dogan Ulus
dblp:137/4307
· DBLP profile ↗
15ranked-venue papers
9as first author
2since 2021 · last 2026
0000-0002-5090-1769ORCID · verified
Domains — the database's venue-derived domains; a paper can count in several
Software engineering, systems software and programming languages · 9 · 5 first-authorTheory of computation · 6 · 3 first-author · 1 since 2021Systems, architecture and hardware · 2 · 2 first-author · 1 since 2021Applied, interdisciplinary, general and emerging computing · 1
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2026 | Online Monitoring of Metric Temporal Logic using Sequential NetworksabstractMetric Temporal Logic (MTL) is a popular formalism to specify temporal patterns with timing constraints over the behavior of cyber-physical systems with application areas ranging in property-based testing, robotics, optimization, and learning. This paper focuses on the unified construction of sequential networks from MTL specifications over discrete and dense time behaviors to provide an efficient and scalable online monitoring framework. Our core technique, future temporal marking, utilizes interval-based symbolic representations of future discrete and dense timelines. Building upon this, we develop efficient update and output functions for sequential network nodes for timed temporal operations. Finally, we extensively test and compare our proposed technique with existing approaches and runtime verification tools. Results highlight the performance and scalability advantages of our monitoring approach and sequential networks. Dogan Ulus |
Log. Methods Comput. Sci. | 1 |
| 2024 | Elements of Timed Pattern MatchingabstractThe rise of machine learning and cloud technologies has led to a remarkable influx of data within modern cyber-physical systems. However, extracting meaningful information from this data has become a significant challenge due to its volume and complexity. Timed pattern matching has emerged as a powerful specification-based runtime verification and temporal data analysis technique to address this challenge. In this paper, we provide a comprehensive tutorial on timed pattern matching that ranges from the underlying algebra and pattern specification languages to performance analyses and practical case studies. Analogous to textual pattern matching, timed pattern matching is the task of finding all time periods within temporal behaviors of cyber-physical systems that match a predefined pattern. Originally we introduced and solved several variants of the problem using the name of match sets, which has evolved into the concept of timed relations over the past decade. Here we first formalize and present the algebra of timed relations as a standalone mathematical tool to solve the pattern matching problem of timed pattern specifications. In particular, we show how to use the algebra of timed relations to solve the pattern matching problem for timed regular expressions and metric compass logic in a unified manner. We experimentally demonstrate that our timed pattern matching approach performs and scales well in practice. We further provide in-depth insights into the similarities and fundamental differences between monitoring and matching problems as well as regular expressions and temporal logic formulas. Finally, we illustrate the practical application of timed pattern matching through two case studies, which show how to extract structured information from temporal datasets obtained via simulations or real-world observations. These results and examples show that timed pattern matching is a rigorous and efficient technique in developing and analyzing cyber-physical systems. Dogan Ulus, Thomas Ferrère, Eugene Asarin, Dejan Nickovic, Oded Maler |
ACM Trans. Embed. Comput. Syst. | 1 |
| 2020 | First-order temporal logic monitoring with BDDs
Klaus Havelund, Doron A. Peled, Dogan Ulus |
Formal Methods Syst. Des. | 3 |
| 2020 | AMT 2.0: qualitative and quantitative trace analysis with extended signal temporal logic
Dejan Nickovic, Olivier Lebeltel, Oded Maler, Thomas Ferrère, Dogan Ulus |
Int. J. Softw. Tools Technol. Transf. | 5 |
| 2019 | Timescales: A Benchmark Generator for MTL Monitoring Tools
Dogan Ulus |
RV | 1 |
| 2019 | Reactive Control Meets Runtime Verification: A Case Study of Navigation
Dogan Ulus, Calin Belta |
RV | 1 |
| 2018 | Embedded software for robotics: challenges and future directions: special sessionabstractThis paper surveys recent challenges and solutions in the design, implementation, and verification of embedded software for robotics. Emphasis is placed on mobile robots, like self-driving cars. In design, it addresses programming support for robotic systems, secure state estimation, and ROS-based monitor generation. In the implementation phase, it describes the synthesis of control software using finite precision arithmetic, real-time platforms and architectures for safety-critical robotics, efficient implementation of neural network based-controllers, and standards for computer vision applications. The issues in verification include verification of neural network-based robotic controllers, and falsification of closed-loop control systems. The paper also describes notable open-source robotic platforms. Along the way, we highlight important research problems for developing the next generation of high-performance, low-resource-usage, correct embedded software. Houssam Abbas, Indranil Saha 0001, Yasser Shoukry, Rüdiger Ehlers, Georgios Fainekos, Rajesh K. Gupta 0001, Rupak Majumdar, Dogan Ulus |
EMSOFT | 8 |
| 2018 | Specifying Timed Patterns using Temporal LogicabstractMonitoring system behaviors using formal specifications appears to be an effective technique in analyzing cyber-physical systems. However, to achieve intended results in monitoring, specification languages need to be intuitive, elegant, and expressive at the first place. In this paper, we propose a metric extension of well-known Halpern-Shoham (hs) logic, called Metric Compass Logic (mcl), for monitoring purposes. Originally proposed for high-level temporal reasoning, the logic hs is very expressive and enables users to specify many temporal patterns in an intuitive and elegant way. As our main contribution, we present an offline monitoring technique for timed patterns specified in mcl. Our solution is built upon the framework developed for timed regular expressions (TRE) matching but explores a different (logical) direction. We finally study several practical features concerning atomic formulas and discuss a combined timed pattern speciication language with TRE. Dogan Ulus, Oded Maler |
HSCC | 1 |
| 2018 | AMT 2.0: Qualitative and Quantitative Trace Analysis with Extended Signal Temporal Logic
Dejan Nickovic, Olivier Lebeltel, Oded Maler, Thomas Ferrère, Dogan Ulus |
TACAS (2) | 5 |
| 2017 | Montre: A Tool for Monitoring Timed Regular Expressions
Dogan Ulus |
CAV (1) | 1 |
| 2017 | First order temporal logic monitoring with BDDsabstractRuntime verification is aimed at analyzing execution traces stemming from a running program or system. The traditional purpose is to detect the lack of conformance with respect to a formal specification. Numerous efforts in the field have focused on monitoring so-called parametric specifications, where events carry data, and formulas can refer to such. Since a monitor for such specifications has to store observed data, the challenge is to have an efficient representation and manipulation of Boolean operators, quantification, and lookup of data. The fundamental problem is that the actual values of the data are not necessarily bounded or provided in advance. In this work we explore the use of Binary Decision Diagrams (BDDs) for representing observed data. Our experiments show a substantial improvement in performance compared to related work. Klaus Havelund, Doron A. Peled, Dogan Ulus |
FMCAD | 3 |
| 2016 | Online Timed Pattern Matching Using Derivatives
Dogan Ulus, Thomas Ferrère, Eugene Asarin, Oded Maler |
TACAS | 1 |
| 2015 | Measuring with Timed Patterns
Thomas Ferrère, Oded Maler, Dejan Nickovic, Dogan Ulus |
CAV (2) | 4 |
| 2013 | Integrating circuit analyses for assertion-based verification of programmable AMS circuits
Dogan Ulus, Alper Sen 0001, Ismail Faik Baskaya |
FDL | 1 |
| 2013 | Analog layer extensions for analog/mixed-signal assertion languagesabstractAssertion-based methodology is gaining popularity in analog and mixed-signal (AMS) verification. Early AMS assertion languages are built on digital assertion languages. This results in limited native support to express most low-level aspects of AMS properties. We present three analog layer extensions to increase analog expressiveness in AMS assertion languages. We first describe the concept of haloes, an implicit way to handle tolerance values of analog signals in assertions. Then, booleanization of analog signals using dual-threshold is introduced to solve problems caused by fluctuations on signals. Finally, we integrate analog measurement operators into assertions. We validate our extensions using our prototype tool on a 10-bit two-stage pipelined analog-to-digital converter design. Dogan Ulus, Alper Sen 0001, Ismail Faik Baskaya |
VLSI-SoC | 1 |