In ultrasound elastography, the noise present in the measured displacement fields has been a critical factor affecting the quality of the strain or elastic distribution reconstruction. Existing partial differential equation (PDE) based denoising algorithms can effectively remove noise to some extent but are limited by slow solving speeds. To address this challenge, we introduce a neural operator-based framework for denoising measured displacement fields in ultrasound elastography. By utilizing neural operators to learn a general solution operator for the denoising equation, the framework aims to achieve fast and accurate denoising of displacement fields. Experiments conducted on simulated data and tissue-mimicking phantom data demonstrate that this method performs comparably to traditional methods across various metrics. In particular, the proposed approach achieves processing speeds approximately 30 to 577 times faster than the finite difference method (FDM) in various data dimensions, making it a highly effective solution for rapid and scalable data processing in ultrasound elastography.

Classic McEliece is a code-based quantum-resistant public-key scheme characterized with relative high encapsulation/decapsulation speed and small ciphertexts, with an in-depth analysis on its security. However, slow key generation with large public key size make it hard for wider applications. Based on this observation, Mckeycutter, a high-throughput key generator in hardware, is proposed to accelerate the key generation in Classic McEliece based on algorithm-hardware co-design. Meanwhile the storage overhead caused by large-size keys is also minimized. First, compact large-size GF(2) Gauss elimination method is presented by adopting naive processing array and memory-friendly scheduling strategy. Second, an optimized constant-time hardware sorter is proposed to support regular memory accesses with less comparators and storage. Third, algorithmlevel pipeline is enabled for high-throughput processing, allowing for concurrent key generations. Our FPGA implementation results achieve around 4× improvements in throughput with 9~14× less memory-time product compared with the existing FPGA solutions.

Aspect-based sentiment analysis (ABSA) is a task of fine-grained sentiment analysis that focuses on discerning the sentiment polarity of a sentence concerning specific aspects. This paper introduces a novel graph convolutional network, denoted as Semantic Dependency and Aspect Interaction Graph Convolutional Network(SDAIGCN), to overcome the limitations of existing graph-based sentiment analysis models in handling the semantic intricacies within aspectual phrases and the sentiment interactions among different aspects in a sentence. The SDAIGCN model achieves this by incorporating internal semantic correlations among aspect phrases through syntactic dependencies between context and aspect words in a sentence. Additionally, it associates affective interactions among different aspects to generate four types of adjacency matrix graphs. Experimental results on four publicly available datasets demonstrate that our proposed model yields improvements in both accuracy and F1 score.

Saber, the only module-learning with rounding-based algorithm in NIST's third round of post-quantum cryptography (PQC) standardization process, is characterized by simplicity and flexibility. However, energy-efficient implementation of Saber is still under investigation since the commonly used number theoretic transform can not be utilized directly. In this manuscript, an energy-efficient configurable crypto-processor supporting multi-security-level key encapsulation mechanism of Saber, is proposed. First, an 8-level hierarchical Karatsuba framework is utilized to reduce degree-256 polynomial multiplication to the coefficient-wise multiplication. Second, a hardware-efficient Karatsuba scheduling strategy and an optimized pre-/post-processing structure is designed to reduce the area overheads of scheduling strategy. Third, a task-rescheduling-based pipeline strategy and truncated multipliers are proposed to enable fine-grained processing. Moreover, multiple parameter sets are supported in LWRpro to enable configurability among various security scenarios. Enabled by these optimizations, LWRpro requires 1066, 1456 and 1701 clock cycles for key generation, encapsulation, and decapsulation of Saber768. The post-layout version of LWRpro is implemented with TSMC 40 nm CMOS process within 0.38 mm2. The throughput for Saber768 is up to 275k encapsulation operations per second and the energy efficiency is 0.15 uJ/encapsulation while operating at 400 MHz, achieving nearly 50× improvement and 31× improvement, respectively compared with current PQC hardware solutions.