This brief is devoted to the development of a switching scheme for unary digital-to-analog converters (DACs). Switching schemes are one of the possible solutions to compensate the influence of the component value deviations appearing during integrated circuit production. Previously known deterministic switching schemes have some weak points, which limit the compensation with resolution growth. In order to overcome such drawbacks, this work adapts the properties revealed and employed in switching schemes, where each element is split into several parts. Based on these properties, the novel hierarchical chessboard flip (HCF) switching scheme is proposed. The simulation demonstrated that HCF reduces the integral nonlinearity (INL) better than previously known solutions while being scalable to any even bit number in DAC array. Adoption to odd resolutions is also possible. Additionally, an extension of the commonly used simulation approach is introduced. Obtaining a dependence of INL reduction on the rotation angle of the error profile may reveal a weakness of some switching scheme in spite of competitive average values.

A search algorithm is presented for a switching scheme with a small number of unit capacitors for a digital-to-analog converter (DAC) used in a successive approximation register (SAR) analog-to-digital converter (ADC). The iterative algorithm is intended to build a binary tree for switching a charge-sharing DAC using a minimum possible number of capacitors. The resulting scheme does not increase the number of clock cycles for the binary search. The relationship between ADC resolution and the number of capacitors proves to be linear, in contrast to an exponential relationship usual for the capacitor arrays. Compared to a previously reported low-power and compact scheme, in a 10-bit case, a 76% reduction in capacitor count is achieved. The simulation results in a 65-nm CMOS technology with a sampling rate of 100 kS/s are presented.