In order to reduce DPPM (defect parts per million), IDDQ testing methodology can be exploited for identifying "outliers" which are potentially defective but not detected by signoff functional and parametric tests. Conventional IDDQ testing paradigms depending on a simple statistical 6σ rule or engineers’ experience are usually too conservative to effectively identify non-trivial outliers, especially when spatial correlations are of great concern/influence. In this paper, by employing a stochastic regression model, the mean as well as the variance of the IDDQ of a die under test (DUT) can be predicted. According to the predicted mean and variance, we derive an expected IDDQ range and identify the DUT as an outlier if its actual IDDQ measurement is beyond the expected range. The proposed stochastic regression model is obtained by training a convolutional neural network (CNN) and, based on its primitive property of convolutional kernel mapping with large volume of industrial data, spatial correlations (due to spatially-correlated process variations, etc) can be considered/captured. The trained data-driven CNN is highly accurate in terms of R-square (0.958) and RMSE (0.783), and the percentage of identified outliers (0.047%) is very close to the theoretical reference (0.050%), which validates the efficacy of our proposed methodology.

To measure the variation of device Vtrequires long test for conventional wafer acceptance test (WAT) test structures. This paper presents a framework that can efficiently and effectively obtain the mean and variance of Vtfor a large number of designs under test (DUTs). The proposed framework applies the model-based random forest as its core model-fitting technique to learn a model that can predict the mean and variance of Vtbased only on the combined Idmeasured from parallel connected DUTs. The proposed framework can further minimize the total number of Idmeasurement required for prediction models while limiting their accuracy loss. The experimental results based on the SPICE simulation of a UMC 28-nm technology demonstrate that the proposed model-fitting framework can achieve a more than 99% R-squared for predicting either Vtmean or Vtvariance. Compared to conventional WAT test structures using binary search, our proposed framework can achieve a 120.3 × speedup on overall test time for test structures with 800 DUTs.

This paper presents a statistical model-fitting framework to efficiently decompose the impact of device Vt variation and power-network IR drop from the measured ring-oscillator frequencies without adding any extra circuitry to the original ring oscillators. The framework applies Gaussian process regression as its core model-fitting technique and stepwise regression as a pre-process to select significant predictor features. The experiments conducted based on the SPICE simulation of an industrial 28nm technology demonstrate that our framework can simultaneously predict the NMOS Vt, PMOS Vt and static IR drop of the ring oscillators based on their frequencies measured at different external supply voltages. The final resulting R squares of the predicted features are all more than 99.93%.

To measure the variation of device Vtrequires long test for conventional WAT test structures. This paper presents a framework that can efficiently and effectively obtain the mean and variance of Vtfor a large number of DUTs. The proposed framework applies the model-based random forest as its core model-fitting technique to learn a model that can predict the mean and variance of Vtbased on only the combined Idmeasured from parallel connected DUTs. The experimental results based on the SPICE simulation of a UMC 28nm technology demonstrate that the proposed model-fitting framework can achieve a more than 99% R-squared for predicting both of Vtmean and variance. Compared to conventional WAT test structures using binary search, our proposed framework can achieve 42.9X speedup in turn of the required iterations of Idmeasurement per DUT.

This paper presents a novel diagnosis technique for multiple defects. This technique proposes a simple heuristic to partition the failures log so that hard-to-detect defects and easy-to-detect defects are likely to be separated. This technique requires only commercial diagnosis software with a simple add-on tool. No customized diagnosis software is needed. Simulations on benchmark circuits demonstrated the effectiveness of the proposed technique. Real silicon experiments on a real industrial product have been verified by physical failure analysis that our technique does not lead to wrong diagnosis for single defect cases.

Through silicon via (TSV) is a widely used interconnect technology in 3-D integrated circuits. This paper shows that defective TSVs can induce small delay faults in surrounding logic gates. We present simulation results of TSV-induced small delay fault (TSDF) because of mechanical stress or pinhole leakage. A test technique is proposed to detect TSDF using a physical-aware fault extractor and timing-aware automatic test pattern generation. This technique requires no DfT area overhead and no direct TSV probing. Experimental results on benchmark circuits show that test coverage can be improved by 22% and 10% for stress-induced and leakage-induced TSDF, respectively. In our results, the test length overheads of both TSDFs are <; 5%.