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Arian Maghazeh

dblp:138/2585 · DBLP profile ↗
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3ranked-venue papers
3as first author
0since 2021 · last 2019
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3 · 3 first-authorSoftware engineering, systems software and programming languages · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
GPUs and heterogeneous computing · 100%
Computer networks
1 paper
Internet architecture and protocols · 100%

Topics — the 4 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Internet architecture and protocols › packet processing
packet classification
0.312017
Latency-Aware Packet Processing on CPU-GPU Heterogeneous Systems · DAC 2017
Internet architecture and protocols
packet processing
0.312017
Latency-Aware Packet Processing on CPU-GPU Heterogeneous Systems · DAC 2017
GPUs and heterogeneous computing › CPU-GPU heterogeneous computing
CPU-GPU heterogeneous systems
0.312017
Latency-Aware Packet Processing on CPU-GPU Heterogeneous Systems · DAC 2017
GPUs and heterogeneous computing
packet processing
0.312017
Latency-Aware Packet Processing on CPU-GPU Heterogeneous Systems · DAC 2017

Methods — techniques the papers use, named apart from their topics

persistent kernel architecture · 0.6
YearPublicationVenuePosition
2019 Cache-Aware Kernel Tiling: An Approach for System-Level Performance Optimization of GPU-Based Applications
abstract
We present a software approach to address the data latency issue for certain GPU applications. Each application is modeled as a kernel graph, where the nodes represent individual GPU kernels and the edges capture data dependencies. Our technique exploits the GPU L2 cache to accelerate parameter passing between the kernels. The key idea is that, instead of having each kernel process the entire input in one invocation, we subdivide the input into fragments (which fit in the cache) and, ideally, process each fragment in one continuous sequence of kernel invocations. Our proposed technique is oblivious to kernel functionalities and requires minimal source code modification. We demonstrate our technique on a full-fledged image processing application and improve the performance on average by 30% over various settings.
Arian Maghazeh, Sudipta Chattopadhyay 0001, Petru Eles, Zebo Peng
DATE1
2017 Latency-Aware Packet Processing on CPU-GPU Heterogeneous Systems
abstract
In response to the tremendous growth of the Internet, towards what we call the Internet of Things (IoT), there is a need to move from costly, high-time-to-market specific-purpose hardware to flexible, low-time-to-market general-purpose devices for packet processing. Among several such devices, GPUs have attracted attention in the past, mainly because the high computing demand of packet processing applications can, potentially, be satisfied by these throughput-oriented machines. However, another important aspect of such applications is the packet latency which, if not handled carefully, will overshadow the throughput benefits. Unfortunately, until now, this aspect has been mostly ignored. To address this issue, we propose a method that considers the variable bit rate of the traffic and, depending on the current rate, minimizes the latency, while meeting the rate demand. We propose a persistent kernel based software architecture to overcome the challenges inherent in GPU implementation like kernel invocation overhead, CPU-GPU communication and memory access overhead. We have chosen packet classification as the packet processing application to demonstrate our technique. Using the proposed approach, we are able to reduce the packet latency on average by a factor of 3.5, compared to the state-of-the-art solutions, without any packet drop.
Arian Maghazeh, Unmesh D. Bordoloi, Usman Dastgeer, Alexandru Andrei, Petru Eles, Zebo Peng
DAC1
2015 Perception-Aware Power Management for Mobile Games via Dynamic Resolution Scaling
abstract
Modern mobile devices provide ultra-high resolutions in their display panels. This imposes ever increasing workload on the GPU leading to high power consumption and shortened battery life. In this paper, we first show that resolution scaling leads to significant power savings. Second, we propose a perception-aware adaptive scheme that sets the resolution during game play. We exploit the fact that game players are often willing to trade quality for longer battery life. Our scheme uses decision theory, where the predicted user perception is combined with a novel asymmetric loss function that encodes users' alterations in their willingness to save power.
Arian Maghazeh, Unmesh D. Bordoloi, Mattias Villani, Petru Eles, Zebo Peng
ICCAD1