Automated design of analog integrated circuits (ICs) involves balancing multiple objectives under process, voltage, and temperature (PVT) variations. An excess of constraints can ensnare algorithms in local optima, while the variations elevate the costs of simulation. To address this challenge, we propose a two-search mode multi-task evolutionary framework to balance objective optimization and constraint satisfaction under variations. Specifically, considering the inherent relationships between objective optimizations and constraint violations, our method adaptively switches between unconstrained surrogate-assisted and constrained simulation-driven search modes. Furthermore, our framework treats PVT variations as a multi-task challenge, facilitating inter-corner knowledge transfer via multi-task evolution, substantially lowering simulation costs. Our framework has been evaluated using two different sensing elements and an amplifier within a 22 nm process. Based on Monte-Carlo simulations, compared to multi-task reinforcement learning, this method attains a 60% to 80% reduction in the relative inaccuracy of sensing elements and accomplishes a 60% decrease in total runtime.

As the design specifications for circuits become increasingly stringent, the demand for automation and intelligence in the sizing of analog integrated circuits (ICs) continues to grow. Algorithms are required to complete circuit optimization tasks under more comprehensive specifications. In this paper, we propose a transferable pole-zero-based transient assertion (PZTA) system. It minimizes the number of high-time-cost transient (Tran) simulations by asserting the stability of the circuit. Furthermore, we utilize a relational graph convolutional network (RGCN) as a function approximator within a reinforcement learning (RL) framework to extract more topological information from the circuits. Experimental results based on the open-source testing suite AnalogGym demonstrate that compared to RGC-NRL before and after embedding the PZTA system, the number of Tran simulations was reduced by 75.68%. Additionally, the assertion accuracy of the model achieved 99.57%.

This paper proposes a single-inductor dual-output (SIDO) buck-boost DC-DC converter that effectively harvests thermoelectric energy in discontinuous conduction mode (DCM). In addition, the proposed emergency power supply mode (EPSM) improves the maximum output power by more than 18%. A storage capacitor (CSTO) recycles the remaining energy in the inductor during off-Time (Toff) to minimize output ripple. Furthermore, a hybrid zero-current detector (H-ZCD) with 800 nW power consumption is designed to reduce power losses. The proposed converter provides two regulation outputs, while achieving a peak efficiency of 87.8% with an input voltage range from 0.1 V to 0.4 V and a load range from 10 μW to 7000 μW.

This paper proposes a temperature sensor designed for wearable devices, featuring high energy efficiency and a wide temperature range. The dual clamps circuit and current subtractor are utilized to generate sensing currents with high sensitivity, thus enhancing the system’s resolution. The current-to-frequency converter (CFC) employs an Edge Detector (ED) to approximate the two-fold output, increasing resolution and reducing frequency errors caused by delay time. By subtracting the digital codes from two 12-bit counters, the circuit’s accuracy and resolution are further improved. The prototype sensor, implemented in a 180 nm process, achieves an inaccuracy of +0.62 °C/-0.78 °C (3σ) from -60 °C to 110 °C, with a resolution of 40 mK in a 2.2 ms conversion time, resulting in a resolution figure of merit (FoM) of 3.9 pJ•K2. The total power consumption is only 1.12 μW.

Recent advances in machine learning (ML) for automating analog circuit synthesis have been significant, yet challenges remain. A critical gap is the lack of a standardized evaluation framework, compounded by various process design kits (PDKs), simulation tools, and a limited variety of circuit topologies. These factors hinder direct comparisons and the validation of algorithms. To address these shortcomings, we introduced AnalogGym, an open-source testing suite designed to provide fair and comprehensive evaluations. AnalogGym includes 30 circuit topologies in five categories: sensing front ends, voltage references, low dropout regulators, amplifiers, and phase-locked loops. It supports several technology nodes for academic and commercial applications and is compatible with commercial simulators such as Cadence Spectre, Synopsys HSPICE, and the open-source simulator Ngspice. AnalogGym standardizes the assessment of ML algorithms in analog circuit synthesis and promotes reproducibility with its open datasets and detailed benchmark specifications. AnalogGym's user-friendly design allows researchers to easily adapt it for robust, transparent comparisons of state-of-the-art methods, while also exposing them to real-world industrial design challenges, enhancing the practical relevance of their work. Additionally, we have conducted a comprehensive comparison study of various analog sizing methods on AnalogGym, highlighting the capabilities and advantages of different approaches. AnalogGym is available in the GitHub repository1. The documentations are also available at2.

This paper presents a single-inductor multi-path hybrid buck converter (SIMP) implemented in 180 nm CMOS process. The proposed SIMP converter reduces the inductor current stress by jointly using the capacitor path and inductor path to supply current to the load, and reduces the inductor voltage stress with two series connected flying capacitors in one phase. Resulting in the inductor DC current and inductor current ripple can be effectively reduced. Therefore, it can relieve significant power loss from a large DC conduction resistance (DCR) of the inductor. Simulation results show that the proposed SIMP obtains a peak efficiency of 96.1% with 250 mΩ DCR inductor, providing maximum output current of 1.6 A in 5 V input and 0.3-1 V output range.

An ultra-low quiescent current CMOS-only voltage reference with load driving capability has been proposed and simulated in a standard 0.18 μm CMOS process in this paper. A gate-voltage compensation loop is used to achieve load driving capability without using an output buffer. In addition, a stacked diode-connected MOS transistor structure has been introduced to reduce the quiescent current as low as 10 nA and achieve process independence. Lastly, based on the CMOS-only structure, the proposed circuit can allow for a load current as high as 1 mA at 0.7 V. The proposed circuit achieves a temperature coefficient of 33.09 ppm/°C within a range from -20°C to 140°C. Besides, a line sensitivity of 0.177%/V and a power supply rejection ratio of -63 dB at 5 Hz are obtained.

This paper presents a capacitively-coupled chopper instrumentation amplifier designed for the analog front end (AFE) of Electrocardiogram monitoring. It employs an embedded DC-servo loop to reduce the input-referred noise (IRN). Additionally, a digital calibration unit is employed to realize large electrode DC offset (EDO) cancellation ability. To prevent the second harmonic ripple, a three-state ripple reduction loop is proposed here. The proposed AFE is implemented in a 180 nm CMOS process and consumes 1.37 μW from a 1.2 V supply with ±95 mV EDO cancellation range. Besides, the IRN from 1 Hz to 200 Hz is 1.68 μVrmswith a noise efficiency factor of 4.87.

The fast-growing development in wearable electronic devices leads to high demand for small-volume, lightweight, and high-efficiency DC-DC power converters, particularly switched capacitor (SC) DC-DC converters. In this paper, we propose a synthesis framework of step-down SC DC-DC power converters to obtain an optimum converter topology under the design constraints of the conversion ratio and a minimum number of capacitors. The proposed rule-based clustering reduction techniques have reduced the search space and sped up the conversion ratio analysis. In the case study of 8:1 converter synthesis, the run-time for conversion ratio analysis is reduced by 1.26$\boldsymbol{\times}$$\boldsymbol{10^6}$. The proposed efficiency optimization method has improved the peak efficiencies of the cascaded 2:1 converter and Fibonacci converter by 4.7% and 12.8%. The proposed framework has identified new topologies and variants of conventional topologies. The variant of cascaded 2:1 converter shows an improvement of 8.2% on peak efficiency.

Process, voltage, and temperature (PVT) variations in chip fabrication or operation pose a significant challenge to the robustness of analog integrated circuits. Existing design techniques for mitigating PVT variations involve analyzing offsets of DC operating points, but this approach often leads to compromises in circuit performance. To address this challenge, we developed a ‘PVT-Transfer’ framework to facilitate knowledge transfer with evolutionary design. Specifically, by cross-operating the circuit parameters under variations, design knowledge is transferred through parameter migration, thus enhancing the robustness of the resultant circuit. In addition, we leverage data-driven learning to discover potential similarities among PVT variations, thereby mitigating negative knowledge transfer. The PVT-Transfer Framework is evaluated on three integrated voltage references and compared with four state-of-the-art circuit sizing methods. Based on post-layout Monte-Carlo simulations, this framework is verified to offer superior performance to existing methods, yielding a 60% reduction in power consumption, an 80% increase in temperature resilience, and up to 70$\times$enhancement in the figure of merit. Further, it leads to a 60% reduction in the number of required circuit simulations and is suitable for parallel computation.

Designing analog integrated circuits (ICs), particularly sensors and reference circuits, requires a significant amount of human expertise and time, largely due to the requirement of maintaining process, voltage, and temperature (PVT) consistency. So far, there has been plenty of work on tuning the circuit to meet the PVT consistency requirements by comparing the offset of the DC operating point, but this inevitably leads to circuit performance degradation. To improve, we propose a ‘PVT-Transfer’ framework that utilizes knowledge transfer among PVT corners through evolutionary multitasking. Specifically, via cross-operating the circuit parameters under different PVT corners, knowledge is transferred through parameter migration to improve the robustness of the circuit. Further, PVT-Transfer employs data-driven learning to identify potential similarities among PVT variations, thereby leading to more cost-effective optimization. This framework is evaluated on two voltage references and compared with four state-of-the-art circuit sizing methods. The post-layout Monte-Carlo simulation results verify that PVT-Transfer outperforms the existing methods. It reduces the number of simulations required by 60% compared to the GCN-RL method. Besides, PVT-transfer achieves up to 10× improvement in the figure of merit over the human design.

An automatic design system for the voltage reference circuit is presented in this paper. The multi-group hierarchical collaborative evolution algorithm is proposed to automatically generate the circuit structures and intelligently optimize the parameters of the circuits. In order to improve the convergence speed and reduce the optimization time, the gradient boosting decision tree (GBDT) algorithm is introduced to establish the circuit prediction model. In this paper, the automatic design of the CMOS reference source circuit is implemented in a standard 0.18μ m process. Compared with previous work, the number of iterations is reduced by 20%, the optimization time is decreased by 20.48%, the line sensitivity and temperature coefficient are improved by 65.42% and 15.47%, respectively, and the circuit power consumption is reduced by 22.50%.

A CMOS-only and multiple-output voltage reference has been proposed and simulated in a standard 0.18 μm CMOS process in this paper. Three reference voltages with their own advantages simultaneously are obtained based on the body bias technology and specific active load. Among the three references, the best temperature coefficient (TC) of 74.8ppm/°C in the range from -20°C to 80°C is obtained without using resistors and specific devices. By introducing amplifier and pushing away the main pole of the circuit, low line sensitivity (LS) of 0.06%/V and high power supply rejection ratio (PSRR) of -73dB at 10Hz are obtained without capacitor. Besides, due to the subthreshold operation, the current is as low as 77nA with a supply voltage down-to 1V.

A pulse train controlled buck converter operating in adaptive pseudo continuous conduction mode (PCCM) is proposed and implemented in this paper. PCCM is self-adapted by using an charge monitoring and NMOS current sensor. Besides, special switch with extra timing is proposed to eliminate voltage spikes caused by PCCM. Simulation results demonstrate that the transient ripple is smaller than 24 mV for a 500 mA load current step at 1 MHz switching frequency when input and output voltages are 5 V and 2 V, respectively, providing a maximum load current of 1 A in the$0.18-\mu \mathrm{m}$CMOS process.

A current-mode DC-DC buck converter with a parallel auxiliary digital-LDO has been proposed and simulated in a$0.18-{\mu}m$CMOS process in this paper. The proposed auxiliary digital LDO can provide both sink current and source current, which improves the transient response by rapidly injecting a positive or negative current into the output to effectively reduce the overshoot/undershoot voltage. Besides, the digital LDO is also activated and provided the out current during the light load to improve the efficiency. Simulation results demonstrate that the transient ripple is smaller than 60 mV with 800 mA load current step and 1 MHz switching frequency when the input and output voltages are 5 V and 3.3 V, respectively. Furthermore, 61% efficiency maintains under 20 mA load current, which is higher than the traditional converters.

A current mode DC-DC buck converter with fast transient response has been proposed and implemented in a commercial 0.4-μm CMOS process in this paper. The fast transient response is obtained by using an amplitude-limited error amplifier with a rapid error-signal control. The proposed fast transient control sets up or down the error signal to the maximum or minimum voltage of the amplifier during the load transient. Thus the duty cycle rapidly decrease or increase to the lowest or highest level the converter could achieve, and the overshoot/undershoot voltage is effectively reduced. Measurement results demonstrate that the transient ripple is smaller than 35 mV for a 450 mA load current step at 1 MHz switching frequency when input and output voltages are 5 V and 1.8 V, respectively. Besides, the converter only occupies an area of 1.3 mm2, providing a maximum load current of 1000 mA.

A sub-1 V and ultra-low power consumption voltage reference has been implemented in a standard 0.18μm CMOS process, without using resistors and special threshold voltage devices. A temperature coefficient (TC) of 37.8 ppm/°C in a temperature range of -40°C~60°C is achieved. The supply voltage ranges from 1 V to 3 V, and the line sensitivity (LS) is 0.02%/V. When VDDis minimum, the supply current measured is 86 nA at room temperature, and the power supply rejection ratios (PSRRs) without any filter capacitor at 100Hz and 10MHz are lower than -56 dB and -9.5 dB, respectively.