Chengyan Zhao

dblp:139/3898 · DBLP profile ↗
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6ranked-venue papers
2as first author
3since 2021 · last 2025
0000-0002-5450-092XORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Artificial intelligence and machine learning · 2 · 1 since 2021Software engineering, systems software and programming languages · 2 · 1 first-author · 2 since 2021Applied, interdisciplinary, general and emerging computing · 2 · 2 first-author · 1 since 2021Systems, architecture and hardware · 1
YearPublicationVenuePosition
2025 L1/L∞-Hankel Norm optimization of Power Wireless Communication Networks by DC Programming
abstract
Distributed power control is crucial for ensuring reliable communication and minimizing energy consumption in wireless communication networks, particularly under random switching topologies and uncertain network dynamics. Existing methods primarily rely on traditional norms or control paradigms, often facing computational challenges due to inherent nonconvexities. In this paper, we propose a novel distributed optimization framework for wireless networks using DC programming to minimize the L1/L∞-Hankel norm of the system. Unlike conventional approaches that may yield suboptimal solutions or suffer from computational inefficiency, the DC programming approach systematically decomposes the nonconvex Hankel norm minimization problem into tractable convex subproblems, ensuring rapid convergence and globally optimal or near-optimal solutions. Our method specifically addresses dynamic topologies modeled by random switching and parameter uncertainties, significantly improving robustness and interference management. Simulation results demonstrate that the proposed framework effectively maintains the desired SINR levels and accelerates convergence of global solution.
Chengyan Zhao, Satoshi Ueno, Bohao Zhu, Wenjie Mei
CoDIT1
2023 Linker Code Size Optimization for Native Mobile Applications
abstract
Modern mobile applications have grown rapidly in binary size, which restricts user growth and hinders updates for existing users. Thus, reducing the binary size is important for application developers. Recent studies have shown the possibility of using link-time code size optimizations by re-invoking certain compiler optimizations on the linked intermediate representation of the program. However, such methods often incur significant build time overhead and require intrusive changes to the existing build pipeline.
Gai Liu, Umar Farooq 0002, Chengyan Zhao, Nian Sun
CC3
2023 Lightweight deep neural network from scratch
Xuebin Yue, Chengyan Zhao, Lin Meng 0001
Appl. Intell.3
2019 Discrete greedy flower pollination algorithm for spherical traveling salesman problem
Yongquan Zhou, Rui Wang 0043, Chengyan Zhao, Qifang Luo, Mohamed A. Metwally
Neural Comput. Appl.3
2016 A Complex Encoding Flower Pollination Algorithm for Global Numerical Optimization
Chengyan Zhao, Yongquan Zhou
ICIC (1)1
2013 Parallel Radix Sort on the AMD Fusion Accelerated Processing Unit
abstract
We design, implement and evaluate a parallel radix sort that simultaneously utilizes the CPU and GPU devices on the AMD Fusion APU. The parallel sort, referred to as Fusion Sort, partitions the sort keys between the CPU and GPU devices and utilizes the integrated memory system of the APU to avoid data copying between the devices. We identify three design issues that impact overhead and performance: the granularity of sharing between the two devices, the scheme of data partitioning and the allocation of data in memory regions accessible by each device. We present three variants of Fusion Sort that share data at coarse and fine granularities and with fixed and variable data partitioning schemes. In each variant, data is allocated to minimize the overhead of non-preferred memory accesses of each device. Our evaluation shows that fine-grain sharing with variable data partitioning performs the best. Further, Fusion Sort outperforms CPU-only and GPU-only parallel radix sorts by up to 1.8X and 1.9X respectively. These results demonstrate the viability of the integrated memory system of the APU in the context of sorting.
Michael C. Delorme, Tarek S. Abdelrahman, Chengyan Zhao
ICPP3