Traditional Chinese medicine(TCM), as a treasure of Chinese culture, still has considerable vitality today. In the treatment of certain diseases such as diabetes mellitus and hypertension, TCM has significant advantages. In practical applications, however, TCM faces certain challenges. For example, the mechanism of action of herbal formulas remains unclear, and prescription issuance is highly dependent on the personal experience of doctors, making it difficult to achieve precise medication targeting specific conditions. This has, to some extent, impacted its credibility. To address these issues, we have developed an AIbased TCM diagnostic assistant called DMease, designed to assist doctors in diagnosing diabetes mellitus. We utilize large language models (LLM) to process multi-source TCM data, constructing SYMPTOM-TARGET-HERB triple knowledge graphs. In addition, we use the Kolmogorov-Arnold Network (KAN) to support prescription formulation. Preliminary experimental results on test data suggest that DMease shows potential to support doctors' diagnostic judgment. Furthermore, our case study illustrates its capability for reducing prescription complexity, warranting further clinical investigation.

With the intelligent multimedia development, it is very common to use artificial intelligence methods to process multimedia data, but the problem of protecting the privacy of data is very critical. This paper focuses on privacy-protected split federated learning in processing images and we propose a framework called MPCSFL, which avoids the transmission of data labels and makes use of secure multi-party computation to enhance privacy protection. Compared with traditional privacy protection methods based on differential privacy, MPCSFL can keep the gradient matching loss above 0.4 in iDLG attack. In the model inversion attack scenario, MPCSFL will not expose the effective information of the raw data when the traditional protection method is cracked, which means that MPCSFL can protect the privacy more effectively.

Number theoretic transform (NTT) is useful for the acceleration of polynomial multiplication, which is the main performance bottleneck in the next-generation cryptographic schemes. Different NTT-based cryptographic algorithms have different security settings. The diverse application scenarios introduce different cost-performance tradeoffs and hardware constraints. Motivated by the emerging demand for more versatile NTT hardware accelerators, we propose a new design methodology that can generate area-efficient and high-performance NTT accelerators for any length and modulus of NTT polynomials and single processing element (PE) or PE array with a varying number of layers. The proposed NTT accelerator architecture pivots on a conflict-free memory access pattern for adaptation to different combinations of security and PE array configuration parameters. The proposed memory access pattern is formally proved to be conflict-free for any parametric configurations. The criterion for read-after-write conflict without pipeline stall is also established. Our proposed design methodology can produce NTT accelerators with single PE or multilayer PE array for different polynomial size and modulus, with hardware area and computational efficiency comparable to accelerators customized for a fixed set of parameters. Our proposed methodology produces parameterized accelerator with higher scalability than the existing parameterized accelerator design. On average, the accelerators generated by our proposed method are 71.4% more area-time efficient. Up to 30.7% area-time reduction over the most area-time efficient state-of-the-art scalable NTT accelerator can be achieved for the same security parameters.

Physical Unclonable Functions (PUF) is an emerging design technology for secure hardware. It exploits the physical manufacturing variations of silicon ICs to generate a unique signature for each chip. A Ring Oscillator (RO) based PUF is a promising solution for the authentication of FPGA devices. However; this technique has not yet been widely adopted due to its large area costs and the lack of platform-independent PUF architectures which are “easy to implement”. Existing RO PUF design requires large number of ring oscillators to generate a relatively safe unique identifier; they also have complex routing requirements. This work proposes a novel configurable RO PUF architecture easily portable between different FPGA platforms. It also offers significantly larger number of challenge-response pairs compared to existing solutions with the same area overheads. The design was realized and characterized using an Altera FPGA device. Experimental results show that the quality of this design conforms to the requirements of general RO PUF.