This paper presents a memristive device model capable of accurately matching a wide range of characterization data collected from a tantalum oxide memristor. Memristor models commonly use a set of equations and fitting parameters to match the complex dynamic conductivity pattern observed in these devices. Along with the proposed model, a procedure is also described that can be used to optimize each fitting parameter in the model relative to an I-V curve. Therefore, model parameters are self-updated based on this procedure when a new cyclic I-V sweep is provided for model optimization. This model will automatically provide the best possible match to the characterization data without any additional optimization from the user. In this paper, multiple cyclic I-V characterizations are modeled from ten different tantalum oxide devices (on the same wafer). Additionally, studies were completed to demonstrate the amount of variation present between devices on a wafer, as well as the amount of variation present within a single device. Methods for modeling this variation are then proposed, resulting in an accurate and complete, automated, memristor modeling approach.

This paper describes memristor-based neuromorphic circuits for non-linear separable pattern recognition. We initially describe a memristor based neuron circuit and then show how multilayer neural networks can be constructed using this neuron circuit. These neuromorphic circuits are capable of learning both linearly and non-linearly separable logic functions. This paper presents the first study of applying neural network learning algorithms to these circuits in SPICE. Our simulations capture alternate current paths within the memristor crossbars and wire resistances that are essential to properly model in crossbar circuits. Our results show that neural network learning algorithms are able to train around these alternate current paths. Further, it was shown that neural networks can properly train the passive memristor-based crossbars without having to use virtual ground mode operational amplifiers as suggested in previous work. Our circuit requires in-situ training, but reduces the number of transistors required by the circuit by about 3 times and reduced the circuit power consumption almost 2 orders of magnitude compared to a virtual ground approach. The key impact of this study is the demonstration through low level circuit simulations that dense memristor crossbars can be effectively utilized to build neuromorphic processors.

This study examines the design of several novel specialized multicore neural processors. Systems based on SRAM cores and memristor devices were examined. Detailed circuit simulations were used to ensure that the systems could be compared accurately. Two types of memristor cores were examined: digital and analog cores. Novel circuits were designed for both of these memristor systems. Additionally full system evaluation of multicore processors based on these cores and specialized routing circuits were developed. Our results show that the memristor systems yield the highest throughput and lowest power. We compared these specialized systems to more traditional HPC systems. Two commodity high performance processors were examined: a six core Intel Xeon processor, and an NVIDIA Tesla M2070 GPGPU. Care was taken to ensure the code on each platform was very efficient (multi-threaded on the Xeon processor, and a high device utilization CUDA program on the GPGPU). Our results indicate that the specialized systems can be between two to five orders more energy efficient compared to the traditional HPC systems. Additionally the specialized cores take up much less die area - allowing in some cases a reduction from 179 Xeon six-core processor chips to 1 memristor based multicore chip and a corresponding reduction in power from 17 kW down to 0.07 W.