This paper presents the major limitations to the interconnect technology scaling at future technology generations and demonstrates both evolutionary and radical potential solutions to the BEOL scaling problem. To address the local interconnect challenges, a novel hybrid Al-Cu interconnect technology is introduced. Performances of carbon-based interconnects are evaluated as a more radical solution. The impact of interconnects and the optimal interconnect options are investigated for emerging next generation devices. Interconnects for new state variables, namely spintronic interconnects, are studied and their potential performances in an all-spin logic system are evaluated.

In this paper, emerging low-power interconnect options for CMOS and beyond CMOS technologies are reviewed. First, electrical interconnects based on carbon nanotubes and graphene nanoribbons are discussed. It is found that carbon-based electrical interconnects can potentially outperform their conventional Cu counterpart at technology nodes close to or below 10 nm. Next, since using electron spin as a novel state variable has attracted major attention, interconnect options for beyond-COMS spintronic devices will be discussed. We start with metallic interconnects based on the non-local spin-valve and spin-torque-driven switching, and the impact of size effects and dimensional scaling on their potential performance is studied. It is found that the spin signal in the non-local structure decays significantly because of a large degradation in the spin relaxation length as the interconnect width decreases. Next, a spintronic interconnect in the form of a conventional spin-valve configuration is introduced to increase the energy efficiency by eliminating the loss of spins in the non-local structure. Both metallic and semiconducting channels are studied, and the results show that the metallic interconnect is more energy-efficient than the semiconducting one when the interconnect is short (a few hundreds of nanometers) due to a high conductive current path. However, a semiconducting channel is appropriate for an intermediate or long (several microns) interconnect due to a longer spin relaxation time and the possibility of using an electric field to enhance the spin relaxation length. Furthermore, it is shown that for spin interconnects, downscaling the size of the ferromagnets can largely reduce the delay, energy, and energy-delay product at the cost of a shorter retention time.

Interconnects are considered as one of the grandest challenges that gigascale and terascale integrations face because of the delay they add to critical paths, the power they dissipate, the noise and jitter they induce on one another, and their vulnerability to electromigration. Recent studies on novel computational state variables such as electron spin have demonstrated that interconnects will continue to be an ever-growing challenge, even for post-complementary metal-oxide-semiconductor (CMOS) switches. The novel 2-D carbon-based material graphene has demonstrated remarkable electrical properties that make it a viable candidate to implement interconnects in both electrical and spintronic domains. In this paper, physical models of the electron transport parameters such as electron mean free path (MFP), diffusion coefficient, mobility, and resistance per unit length are presented for both bulk (2-D) and narrow (1-D) graphene nanoribbons (GNRs) as a function of the interconnect dimensions, edge roughness, and Fermi-energy shift. The potential of multilayer GNR (ML-GNR) as electrical interconnects is explored by taking into account the finite interlayer resistivity between the multiple layers within the ML-GNR stack. The spin-relaxation length in graphene is obtained using some theoretical estimates on the spin-orbit coupling (SOC) introduced due to ripples in graphene. It is found that, in pure graphene, the spin-relaxation length could be longer than 10 μm; however, the presence of adatoms limits the spin-relaxation length in graphene to only 1-2 μm at room temperature. The models developed in this paper are used to benchmark graphene interconnects against their conventional copper/low- κ interconnects in both electrical and spintronic domains. The results offer important insights about the advantages and limitations of graphene interconnects and provide guidelines for technology development for this emerging interconnect technology.