Advances in semiconductor technology and design automation, together with increased market competition, have driven engineers to achieve higher levels of integration, with shortened development cycles. Consequently, verification and analysis are becoming a major bottleneck for timely design of complex systems. The panelists and the audience will explore silicon debug and its impact on the design cycle.

This paper discusses some of the critical issues that may prevent IEEE P1500 from becoming an acceptable standard and offers some suggestions for their solution. In particular, the inadequacy of the proposed P1500 and the VSIA solutions in handling hierarchical implementations is addressed. Support for hierarchical implementations is seen as an essential feature in a test access methodology that is intended for use in System on a Chip (SoC) designs. The author is actively pursuing some of these solutions through the working groups.

Techniques are described that target extending usability of exiting scan-based DFT approaches for activities beyond IC component testing. In particular, the need for applying DFT to improve product Time-to-Market is described and justified. This need is evident from observations that a System on a Chip (SoC) design poses serious design verification challenges that may impact overall product success in ways that can not be compensated for by improving product quality. DFT features are described that that bring system-level diagnostics tools, such as the system Logic Analyzer and the Service Processor, to the IC level in order to facilitate post-silicon debug and verification. Finally, it is pointed out that much work remains to be done by existing EDA companies (or new entrepreneurial companies) to provide new tools that integrate the new DFT features into the SoC synthesis flow.

This paper proposes a framework to help designers understand how to integrate customized design for test features under the guidelines of the 1149.1 standard. The paper begins by discussing the reasoning behind some of the essential features of the IEEE 1149.1 boundary scan standard. Following that, arguments are made for allowing greater flexibility within the standard in order to accommodate design features, that may follow the intent of the standard but not necessarily the letter of its specification. An example of such a feature is to allow I/O cells in which test logic is "shared" with functional logic. The proposed framework for compatibility with the IEEE 1149.1 standard may result in some changes to the current standard. The framework is intended to provide a guideline for additional tools and recommendations to be developed by the IEEE 1149.1 working group and EDA companies in order to help produce testable designs. The framework also helps to explain and understand the ramifications of implementing testability features, which are not compliant with the boundary-scan standard.

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1. Abstract This paper describes a novel flip-flop design which is used in performing internal path-delay test and measurement using scanpath technique:;. Also described is the design for a boundary-scan cell that enables inpUtlOUtpUt delays to be measured. The paper includes a real-life application example.

The architecture and some of the specific features of a scan-and-clock resource (SCR) chip are described. This chip is used in a high-end workstation product to provide access to the testability features of the individual chips and or printed circuit boards. The chip is designed to be included on each system board and is capable of controlling up to eight independent scan ports. By careful examination of different scan styles, it was discovered that there are two basic styles of scan, differentiated by their clocking mechanisms. The SCR chip uses a mode bit to specify the scan style for each port separately and by so doing to convert from the actual scan style to an internal style so that actual chip characteristics are hidden from the scan/diagnostics software. It is pointed out that using a board-level controller to gain access to the testability features of system components and interfacing the controller to a diagnostics processor (or external tester) are emerging as a common strategy for designing testable digital systems. On the basis of experience gained from such an application, controller features which are deemed useful are discussed.>

An architecture for implementing scan technology for test and debug in a state-of-the-art workstation is described. Architectural features include controlling the scan and clock functions from a single resource that can also perform LFSR (linear feedback shift register) based pseudorandom testing and test result compression via signature capture. Operations of the scan subsystem are controlled from a service processor that uses a diagnostics bus to communicate with individual scan and clock resource units present on each system board. For debug purposes the service processor has been linked with a remote computer, and software has been developed to display and/or modify system state variables (flip-flops). Analysis of scan overhead indicates that benefits in test and debug of the target system far outweight the cost of implementing scan technology for the APOLLO DN10000 workstation.>

Article Free Access Share on ATLAS/ELA: scan-based software tools for reducing system debug time in a state-of-the-art workstation Authors: B. I. Dervisoglu APOLLO Computer Inc., 330 Billerica Rd., Chelmsford, MA APOLLO Computer Inc., 330 Billerica Rd., Chelmsford, MAView Profile , M. A. Keil APOLLO Computer Inc., 330 Billerica Rd., Chelmsford, MA APOLLO Computer Inc., 330 Billerica Rd., Chelmsford, MAView Profile Authors Info & Claims DAC '89: Proceedings of the 26th ACM/IEEE Design Automation ConferenceJune 1989 Pages 718–721https://doi.org/10.1145/74382.74512Online:01 June 1989Publication History 3citation154DownloadsMetricsTotal Citations3Total Downloads154Last 12 Months2Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF

An architecture for implementing scan technology for test and debug in a state-of-the-art workstation is described. Architectural features include controlling the scan and clock functions from a single resource which can also perform linear-feedback shift-register-based pseudorandom testing and test-result compression by signature capture. Operations of the scan subsystem are controlled from a service processor which uses a diagnostics bus to communicate with individual scan and clock resource units present on each system board. For debug purposes the service processor has been linked with a remote computer and software has been developed to display and/or modify system state variables (flip-flops). Analysis of scan overhead indicate that benefits in test and debug of the target system far outweigh the cost of implementing scan technology for the APOLLO DN 10000 workstation.>

Microprogramming has become a widely used technique which brings versatility to the control unit of a digital system. However, since all microcommands contained in a microinstruction are changed simultaneously, this form of control requires the coding of all possible combinations of parallel commands as separate microinstructions. This causes the resulting microprograms to become space- and timewise inefficient and makes it very difficult to control and/or synchronize independent processes. A new approach to modeling and implementing the flow of control in hardware systems is presented in this paper. Here a control flow is realized by a set of independent control operators that pass control to each other according to the precedence relationships defined by the control function which is implemented. The detailed architecture of a VLSI chip to implement a control unit as a hard- programmable control unit (HPCU) is also given. An HPCU contains many independent control operators and allows mask-programmable connections to be made among the operators to implement any given control function. Examples included in the paper demonstrate the effectiveness of an HPCU in implementing complex parallel control flows.

A mixed mode sequential machine (MSM) is defined as a representation in which both synchronous (clocked) and asynchronous (unclocked) state transitions are allowed. The intent of the representation is to allow designers to consider both types of transitions in a single structure, thereby promoting the use of LSI devices such as ROM's or PLA's to resolve the realization question. The approach is thus different from conventional design methods, in which asynchronous problems are treated separately with separate devices. The problems of state reduction, state assignment, and realization are covered. Of particular note is the development of a ROM implementation, which allows both clocked and unclocked transitions to occur.