A new scheme for the automated design and optimization of electromagnetic energy harvesters is presented. The proposed method aims to deal with the limitations of current design techniques and to improve the efficiency of the design process. Most of the current design approaches require significant user experience and knowledge to make informed design decisions, which means that a large amount of time is needed to obtain the optimized design. Additionally, the design solution is suitable only for a specific application, which makes it difficult to adopt it to other application demands. In the proposed method, the development cycle has been sped up significantly by minimizing human efforts and utilizing a generic model for the design process. The method is based on a generic template based on specific resources and requirements, which is processed by a black-box optimization algorithm to come up with a number of promising configuration suggestions. The method's effectiveness and its autonomous operation are demonstrated based on the design optimization of an electromagnetic pick-up unit for vibration energy harvesters using a Halbach array.

Wireless sensor nodes in state of the art fluid power systems used in monitoring and maintenance prediction demand long lasting power sources that do not rely on batteries. Energy harvesting is a promising technology that can provide the required energy to power wireless sensors. Pressure fluctuation energy harvesters can be employed in conventional hydraulic systems to convert the acoustic pressure fluctuation to electrical power. Present studies have explored the overall efficiency of these devices while experimentally describing losses in piezoelectric and circuit interfaces, nevertheless there is no study on the fluid to mechanical force transmission efficiency. In this paper we investigate the pressure to force transmission rate of two types of fluid to mechanical interfaces: a flat metal plate and a conventional hydraulic piston. The interfaces are investigated in conditions similar to those found in conventional hydraulic systems. The study shows that flat plate exhibit good force transmission for low pressure applications with a constant rate across frequencies, while exhibiting a decrease in force transmission at higher pressures. On the other hand the piston exhibit a more robust pressure design, with a constant force transmission rate at all pressures but with a dampening of force at higher frequencies. It is shown that small differences in force transmission ratios can have a considerable impact on the power generation.

Rapid development of extremely-low voltage high current MOSFETs allows reversing common design principles to explore new applications, such as battery powered traction drives. This enables the usage of multi-phase single-turn stator windings which can achieve a copper fill factor close to one. This paper briefly describes the proposed 2V, 1.1kW MOSFET commutated 13-phase permanent magnet DC motor and presents the efficiency and resistive loss measurements of the first prototype. The motor was successfully run with drive currents up to 520 A. Most of the obtained losses were resistive contact losses due to the flexible winding connections, less than 6% are dedicated to the MOSFETs. The results show that such a high current drive system is feasible and has great potential for further improvements, which is supported by the rapid development of extremely-low voltage high current semiconductors.

To verify the FEM simulation of the air-gap flux density, it is necessary to measure the flux density distribution as function of the angular machine position. This paper presents a scalable 3-D direct air-gap flux density magnitude measurement system for rotating electrical machines. A combination of eight linear Hall effect flux sensors and a rotary encoder is used to measure the flux density magnitude as function of the angular machine position. The system is designed for permanent magnet motors with an air gap of at least 1 mm, but can also be used for other types of machines. The miniaturized sensor array with the flux sensors is 0.7 mm thick, and measures the distribution of the air-gap flux density magnitude in a range of ±2 T along the rotor axis. The design of the measurement system is described and tested on a prototype of an electronically commutated permanent magnet DC motor. The obtained measurement results are compared with the FEM simulation results of the prototype motor. A good match between the simulated and measured flux density magnitude is shown. The conclusions presented in this study, are used to further optimize the simulation model and the prototype motor.

Many wireless vision sensor networks (WVSNs) applications are characterized to have a low duty cycling. An individual wireless vision sensor node (VSN) in WVSN is required to complete the tasks as quickly as possible. The execution of the tasks can be speeded up by exploiting the inherited parallelism in the tasks by using a hardware platform such as field-programmable gate array (FPGA). Traditionally, SRAM FPGAs are considered to be inefficient for duty cycled applications. This paper presents a low-complexity, energy-efficient, and reconfigurable VSN architecture based on SRAM FPGA using a design matrix, which includes tasks' partitioning, a low-complexity background subtraction, bilevel coding, and duty cycling. The proposed VSN, referred to as SENTIOF-CAM, has been implemented on a prototype board and energy values of different states are measured for three real applications. The comparison results with existing solutions show that the proposed architecture with SRAM FPGA can achieve energy reduction of up to a factor of 69 as compared with software VSN solutions and approximately similar energy values to that for the FLASH FPGA-based VSN solutions. The lifetime based on measured energy values shows that, for a sample period of 5 min, a 3.2-years lifetime can be achieved with a battery of 37.44-kJ energy. In addition, the proposed solution offers a generic architecture with a smaller design complexity on a hardware reconfigurable platform and offers easy adaptation for a number of applications.

Solar energy harvesting gains more and more attention in the field of wireless sensor networks. In situations, where these sensor systems are deployed outdoors, powering sensor nodes by solar energy becomes a suitable alternative to the traditional way of battery power supplies. Since solar energy, opposed to batteries, can be considered as an inexhaustible energy source, scavenging this source allows longer system lifetimes and brings wireless sensor networks closer to be an autonomous system with perpetual lifetime. Despite the possibility of designing and constructing these harvesting system, dimensioning becomes a crucial task to fit implemented components to application and load system demands. In this paper we present a way of dimensioning solar harvesting systems based on simulation. Method and implementation of component and system models are described on the basis of an example architecture that has been used in prior work. Furthermore we evaluate the model in comparison to deployment of the same architecture and show the suitability of using the simulation as a support to optimize choices for system parameters.

In this paper, a new, real-time reconfigurable perceptron circuit element is presented. A six-transistor version used as a threshold gate, having a fan-in of three, producing adequate outputs for threshold of T =1, 2 and 3 is demonstrated by chip measurements. Subthreshold operation for supply voltages in the range of 100-350 mV is shown. The circuit performs competitively with a standard static complimentary metal-oxide-semiconductor (CMOS) implementation when maximum speed and energy delay product are taken into account, when used in a ring oscillator. Functionality per transistor is, to our knowledge, the highest reported for a variety of comparable circuits not based on floating gate techniques. Statistical simulations predict probabilities for making working circuits under mismatch and process variations. The simulations, in 120-nm CMOS, also support discussions regarding lower limits to supply voltage and redundancy. A brief discussion on how the circuit may be exploited as a basic building block for future defect tolerant mixed signal circuits, as well as neural networks, exploiting redundancy, is included.

For digital circuits with ultra-low power consumption, floating-gate circuits (FGMOS) have been considered to be a potentially better technique than standard static CMOS circuits. By having a DC offset on the floating gates, the effective threshold voltage of the floating-gate transistor is adjusted and the speed and power performance can be altered. In this paper we have investigated how the floating-gate capacitances can be selected to achieve the best performance in floating-gate circuits operating at subthreshold power supply. Based on circuit simulations in a 120nm process technology, it is shown that the EDP offers a reduction of more than one order of magnitude for FGMOS with capacitance selection in comparison to static CMOS circuits. This paper also deals with the possibilities available for trade-offs between lower power consumption and higher speed to achieve a better performance for FGMOS than for static CMOS. The main cost involved in achieving these performance improvements is reduced noise margins

We propose a coding algorithm called unary prefixed Huffman (UPH) coding for a family of infinite sources called quantized generalized Gaussian (GG) sources. Compared with the existing codes for these GG sources, the UPH algorithm provides a more adaptive approach, and its coding efficiency is upper bounded by entropy +2.

Finite state machine (FSM) partitioning proves effective for power optimization. In this paper we propose a design model based on mixed synchronous/asynchronous state memory that results in implementations with low power dissipation and low area overhead for partitioned FSMs. The state memory here is composed of the synchronous local state memory and asynchronous global state memory, where the former is used to distinguish the states inside a sub-FSM, and the latter is responsible for controlling sub-FSM communication. The input and output behaviour of the decomposed FSM is cycle by cycle equivalent to the undecomposed synchronous FSM. Together with clock gating technique, substantial power reduction can be demonstrated.

We present an idea for a new real-time reconfigurable perceptron, also called, a threshold element. The circuit example contain three inverters with shorted outputs. SPICE simulations for a 0.6 /spl mu/m CMOS implementation operating in the subthreshold region. are shown. The threshold voltages of the active devices, seen from driving nodes, may be dynamically changed by adjusting their substrate potentials. This enables a change of the threshold of the perceptron circuit in real-time. In terms of Boolean logic the functionality may be changed between 3-input NOR, CARRY' for the FULL-ADDER function and 3-input NAND, in real-time.

Variable length code (VLC) is used in a large variety of lossless compression applications. A specially designed VLC, called "universal variable length code" (UVLC), is utilized in the latest video coding standard H.26L under development. In this work we propose a new coding method under the name "alternating coding" (ALT coding) and apply it to the UVLC. The ALT coded UVLC yields the same high coding efficiency as the original UVLC, but ALT coding also enables immediate decoding, immediate error detection and location in a UVLC packet. It improves the error resiliency and error robustness of the UVLC packet by applying an "error speculation". Results show that the ALT coded UVLC packet always outperforms the original UVLC packet in terms of error resiliency and robustness. Moreover, the simple pattern of ALT coded UVLC can greatly simplify the UVLC decoder architecture and therefore enables small, fast, and low-power decoder design.

This paper describes the implementation of an asynchronous self-timed direct sequence spread spectrum radio receiver. The designed receiver is planned to be used in MINT [l] (Mobile InterNet Router) radio interface for broadband wireless datacommunication. The receiver has been implemented in a 0.8 pm CMOS technology using a standard cell library. The final design contains approximately 100 OOO transistors.