In this article, we propose a novel model checking-based methodology that analyzes the hardware trojan (HT)-based security vulnerabilities in sequential circuits with 100% coverage while addressing the state-space explosion issue and completeness issue. In this work, the state-space explosion issue is addressed by efficiently partitioning the larger state space into corresponding smaller state spaces to enable the distributed HT-based security analysis of complex sequential circuits. We analyze multiple ISCAS89 and trust-hub benchmarks for different ASIC technologies, i.e., 65, 45, and 22 nm, to demonstrate the efficacy of our framework in identifying HT-based security vulnerabilities. The experimental results show that ForASec successfully performs the complete analysis of the given complex and large sequential circuits, and provides approximately$6\times $–$10\times $speedup in analysis time compared to the state-of-the-art model checking-based techniques.

Conventional Hardware Trojan (HT) detection techniques are based on the validation of integrated circuits to determine changes in their functionality, and on non-invasive side-channel analysis to identify the variations in their physical parameters. In particular, almost all the proposed side-channel power-based detection techniques presume that HTs are detectable because they only add gates to the original circuit with a noticeable increase in power consumption. This paper demonstrates how undetectable HTs can be realized with zero impact on the power and area footprint of the original circuit. Towards this, we propose a novel concept of TrojanZero and a systematic methodology for designing undetectable HTs in the circuits, which conceals their existence by gate-level modifications. The crux is to salvage the cost of the HT from the original circuit without being detected using standard testing techniques. Our methodology leverages the knowledge of transition probabilities of the circuit nodes to identify and safely remove expendable gates, and embeds malicious circuitry at the appropriate locations with zero power and area overheads when compared to the original circuit. We synthesize these designs and then embed in multiple ISCAS85 benchmarks using a 65nm technology library, and perform a comprehensive power and area characterization. Our experimental results demonstrate that the proposed TrojanZero designs are undetectable by the state-of-the-art power-based detection methods.

Photoplethysomographic (PPG) signal is crucial for non-invasive monitoring of heart rate. It is acquired by using pulse oximeter that are prone to artifacts. A major application of this technique is monitoring the heart rate during physical exertion. Extraction of heart rate (HR) from the PPG in this case is difficult due to the strong motion related artifacts. This paper proposes an efficient method based on a reference generation using singular value decomposition and then multistage application of filtered X-LMS for removing motion artifacts from PPG signal. Simultaneous three-axis acceleration data is acquired and used as reference signal to measure time and extent of motion artifact in PPG signal. This is followed by an application of Slope Sum Method (SSM) to track peaks, and thus determine the heart rate. Testing of proposed method on PPG signals acquired from multiple subjects performing intense exercises (jogging at an average speed of 12 km/hour), results in mean absolute error of 1.37 beats per minute (BPM). Moreover, it is shown that proposed algorithm is robust to excessive occurrence of motion artifacts.

This paper presents area-power efficient architectures for the lifting based Wavelet Packet Transform (WPT). Using Daubechies 6 as an example, three different approaches to the lifting scheme implementation are optimized. For higher level decompositions, a novel Fibonacci based technique to optimally compute the number of processing elements per level is presented. Comparisons between FPGA implementations of various architectures show a throughput-to-power ratio improvement of 62% over previously implemented WPT architectures. The architecture consumes a smaller area, while consuming a dynamic power of 46mW at a maximum throughput of 342 Mbits/sec per level.

Inductively coupled transceivers (ICT) are widely being employed in implantable biomedical devices for wireless communication with the external world. The performance of such implant-to-body-surface communication is dependent on the characteristics of the transmitter, the receiver and the channel between them, which consists of layers of biological tissue. In this paper a representative ICT has been studied to characterize the effect of different physical orientations on the bit error process. The effect of biological tissue on the communication channel has also been quantified. The channel was measured to have a bit-level memory of 3 bits and a packet level memory of 6 packets. The impact of forward error correction (FEC) was analyzed and the use of 3-bit FEC was found to reduce the number of retransmissions by 65%. The results of this study enable optimization of reliable implantable communication systems.

Multi-channel neural signal recordings need high data compression and efficient data transmission. Our previous work has shown a practical data compression solution based on discrete wavelet transform, multi-level thresholding and run length encoding. This paper presents a custom designed communication protocol for bidirectional data telemetry to and from the implanted module. A global controller is also presented which configures, operates and unites all the modules together effectively and efficiently into a 32-channel system. Performance of the communication protocol and the compression engine is analyzed.

Neural recordings from high-density microelectrode arrays implanted in the cortex require time-frequency domain processing to alleviate the data telemetry bottlenecks of bandwidth and power. Our previous work has shown that the energy compaction capability of the discrete wavelet transform (DWT) offers a practical data compression solution that faithfully preserves the information in the neural signals. This paper presents a complete compression system including both lossy and lossless compression schemes, namely the DWT and run length encoding. Performance tradeoffs and key design decisions for implantable applications are analyzed. A 32-channel, 4-level version of the circuit is presented. Custom designed in 0.5 mum CMOS, occupying only 5.75 mm2and consuming 3mW of power (95 muW per channel at 25Ks/sec), the implantable compression circuit is well suited for intra-cortical neural interface applications.

Discrete wavelet transform (DWT) has been shown to provide exceptionally efficient data compression for neural records. This paper describes an area-power minimized hardware implementation of the lifting scheme for multi-level, multi-channel DWT. Performance tradeoffs and key design decisions for implantable neuroprosthetics are analyzed. A 32-channel, 4-level version of the circuit has been custom designed in 0.18μm CMOS and occupies only 0.16mm2.