Demo Data from VLDB 2026 / reviewers in the wild / expert
Peter T. Breuer
dblp:14/3633
· DBLP profile ↗
23ranked-venue papers
17as first author
0since 2021 · last 2018
0000-0003-2296-6175ORCID · verified
Domains — the database's venue-derived domains; a paper can count in several
Software engineering, systems software and programming languages · 17 · 13 first-authorSecurity and privacy · 3 · 3 first-authorSystems, architecture and hardware · 2 · 1 first-authorTheory of computation · 2 · 2 first-authorComputer networks · 1Databases, data management, data science and information retrieval · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Electronic design automation · 100% | |
| Theoretical computer science
2 papers |
Logic in computer science · 75% Automata and formal languages · 25% | |
| Software engineering, system software, and programming languages
1 paper |
Compilers and program optimization · 100% |
Topics — the 8 heaviest of 8, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation
hardware description language |
0.0 | 1 | 1997 | A Refinement Calculus for the Synthesis of Verified Hardware Descriptions in VHDL · ACM Trans. Program. Lang. Syst. 1997 |
Electronic design automation › hardware verification and test
hardware verification |
0.0 | 1 | 1997 | A Refinement Calculus for the Synthesis of Verified Hardware Descriptions in VHDL · ACM Trans. Program. Lang. Syst. 1997 |
Electronic design automation › hardware description language
VHDL |
0.0 | 1 | 1997 | A Refinement Calculus for the Synthesis of Verified Hardware Descriptions in VHDL · ACM Trans. Program. Lang. Syst. 1997 |
Logic in computer science › program logic
hoare logic |
0.0 | 1 | 1997 | A Refinement Calculus for the Synthesis of Verified Hardware Descriptions in VHDL · ACM Trans. Program. Lang. Syst. 1997 |
Logic in computer science
program logic |
0.0 | 1 | 1997 | A Refinement Calculus for the Synthesis of Verified Hardware Descriptions in VHDL · ACM Trans. Program. Lang. Syst. 1997 |
Compilers and program optimization
compiler correctness |
0.0 | 1 | 1994 | Decompilation: The Enumeration of Types and Grammars · ACM Trans. Program. Lang. Syst. 1994 |
Compilers and program optimization
decompilation |
0.0 | 1 | 1994 | Decompilation: The Enumeration of Types and Grammars · ACM Trans. Program. Lang. Syst. 1994 |
Automata and formal languages
formal grammars |
0.0 | 1 | 1994 | Decompilation: The Enumeration of Types and Grammars · ACM Trans. Program. Lang. Syst. 1994 |
Methods — techniques the papers use, named apart from their topics
refinement · 0.0formal semantics · 0.0functional programming · 0.0abstract interpretation · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2018 | On Security in Encrypted Computing
Peter T. Breuer, Jonathan P. Bowen, Esther Palomar, Zhiming Liu 0001 |
ICICS | 1 |
| 2017 | On Obfuscating Compilation for Encrypted ComputingabstractCopyright © 2017 by SCITEPRESS - Science and Technology Publications, Lda. All rights reserved. This paper sets out conditions for privacy and security of data against the privileged operator on processors that 'work encrypted'. A compliant machine code architecture plus an 'obfuscating' compiler turns out to be both necessary and sufficient to achieve that, the combination mathematically assuring the privacy of user data in arbitrary computations in an encrypted computing context. Peter T. Breuer, Jonathan P. Bowen, Esther Palomar, Zhiming Liu 0001 |
SECRYPT | 1 |
| 2016 | A Practical Encrypted MicroprocessorabstractCopyright © 2016 by SCITEPRESS - Science and Technology Publications, Lda. All rights reserved.This paper explores a new approach to encrypted microprocessing, potentiating new trade-offs in security versus performance engineering. The coprocessor prototype described runs standard machine code (32-bit OpenRISC v1.1) with encrypted data in registers, on buses, and in memory. The architecture is 'superscalar', executing multiple instructions simultaneously, and is sophisticated enough that it achieves speeds approaching that of contemporary off-the-shelf processor cores. The aim of the design is to protect user data against the operator or owner of the processor, and so- called 'Iago' attacks in general, for those paradigms that require trust in data-heavy computations in remote locations and/or overseen by untrusted operators. A single idea underlies the architecture, its performance and security properties: it is that a modified arithmetic is enough to cause all program execution to be encrypted. The privileged operator, running unencrypted with the standard arithmetic, can see and try their luck at modifying encrypted data, but has no special access to the information in it, as proven here. We test the issues, reporting performance in particular for 64-bit Rijndael and 72-bit Paillier encryptions, the latter running keylessly. Peter T. Breuer, Jonathan P. Bowen, Esther Palomar, Zhiming Liu 0001 |
SECRYPT | 1 |
| 2015 | Processor Rescue - Safe Coding for Hardware Aliasing
Peter T. Breuer, Jonathan P. Bowen, Simon Pickin 0001 |
SoMeT | 1 |
| 2014 | Open source verification in an anonymous volunteer network
Peter T. Breuer, Simon Pickin 0001 |
Sci. Comput. Program. | 1 |
| 2007 | Verification in the Light and Large: Large-Scale Verification for Fast-Moving Open Source C Projects
Peter T. Breuer, Simon Pickin 0001 |
SEW | 1 |
| 2006 | Verification in the Large via Symbolic ApproximationabstractThis article describes the technique,symbolicapproximation, that we have evolved to handle the post-hoc verification of C code in very large open source projects such as the Linux kernel, essentially consisting of deliberate approximation in a symbolic domain. Using the technique, we are treating millions of lines of C code source in a few hours on very modest support platforms. The theoretical foundation is a configurable compositional programming logic and a notion of approximation that is tied to what can be deduced about a program, in that adjusting the logic for reasoning about it adjusts the goodness of the approximation to it. Peter T. Breuer, Simon Pickin 0001 |
ISoLA | 1 |
| 2006 | Detecting Deadlock, Double-Free and Other Abuses in a Million Lines of Linux Kernel SourceabstractThe formal analysis described here detects two so far undetected real deadlock situations per thousand C source files or million lines of code in the open source Linux operating system kernel, and three undetected accesses to freed memory, at a few seconds per file. That is notable because the code has been continuously under scrutiny from thousands of developers' pairs of eyes. In distinction to mo del-checking techniques, which also use symbolic logic, the analysis uses a "3-phase" compositional Hoare-style programming logic combined with abstract interpretation. The result is a customisable post-hoc semantic analysis of C code that is capable of several different analyses at once Peter T. Breuer, Simon Pickin 0001, María M. Larrondo-Petrie |
SEW | 1 |
| 2006 | Raiding the Noosphere: the open development of networked RAID support for the Linux kernelabstractThe Noosphere is a term borrowed by open-source advocate Eric Raymond to denote the virtual world of the Internet. Fitting a new driver into the Linux kernel requires a ‘noospheric’ strategy as well as an engineering strategy, because the code is part of the open-source development process, not its end. This article recounts the technology and the development process followed for a ‘fast and intelligent’ driver extension to the existing Linux software RAID subsystem. The development adapts the kernel RAID subsystem for use in the context of network-attached storage. Copyright © 2005 John Wiley & Sons, Ltd. Peter T. Breuer, Marisol García-Valls |
Softw. Pract. Exp. | 1 |
| 2003 | Fault-Tolerant Distributed Mass Storage for LHC ComputingabstractIn this paper we present the concept and first prototyping results of a modular fault-tolerant distributed mass storage architecture for large Linux PC clusters as they are deployed by the upcoming particle physics experiments. The device masquerading technique using an Enhanced Network Block Device (ENBD) enables local RAID over remote disks as the key concept of the ClusterRAID system. The block level interface to remote files, partitions or disks provided by the ENBD makes it possible to use the standard Linux software RAID to add fault-tolerance to the system. Preliminary performance measurements indicate that the latency is comparable to a local hard drive. With four disks throughput rates of up to 55MB/s were achieved with first prototypes for a RAIDO setup, and about 40M/s for a RAID5 setup. Arne Wiebalck, Peter T. Breuer, Volker Lindenstruth, Timm M. Steinbeck |
CCGRID | 2 |
| 2003 | A Formal Model for the Block Device Subsystem of the Linux Kernel
Peter T. Breuer |
ICFEM | 1 |
| 2003 | Building Wrapper Agents for the Deep Web
Vicente Luque Centeno, Luis Sánchez-Fernández 0001, Carlos Delgado Kloos, Peter T. Breuer, Fernando Paniagua Martín |
ICWE | 4 |
| 2003 | MSC-based Language for Specifying Automated Web ClientsabstractProgramming automated web navigation assistants, i.e., applications that automatically navigate the web performing specific tasks for the user, is far from easy. Since HTML pages offered by legacy web-based applications, which are designed to be manipulated only by people using browsers, web pages contain semi-structured information [P. Atzeni, et al., 1997] whose data schema can easily be changed, the creation and even the maintenance of this kind of applications, is very expensive. However, an increasing amount of information sources and online applications have been added to the web during the last few years, so assistants for automating tasks over those web-enabled applications are more and more needed. These assistants may automate tasks by filling in forms, following links, analyzing data embedded in web pages and performing computations over those data on behalf of the user. Software engineering techniques are clearly needed to reduce the cost, not just creating these programs (by significantly reducing their time-to-market), but even more importantly, maintaining them working properly, reducing the cost of readapting them to web site pages whose structure or navigation schemes are frequently changed. This paper proposes the well known formal method message sequence charts (MSC) [ITU-T, 1997] as a base for defining a language for programming web navigation assistants which may navigate a web site according to the user's aims. This specification language, called XPlore, is specially suited for both requirements engineering and automatic generation of an executable, and has been successfully tested on several well known web sites. Vicente Luque Centeno, Peter T. Breuer, Luis Sánchez-Fernández 0001, Carlos Delgado Kloos, Juan Antonio Herráiz Pérez |
ISCC | 2 |
| 1999 | Reasoning about VHDL and VHDL-AMS using Denotational SemanticsabstractThis paper introduces a denotational semantics for a core of the draft IEEE standard analog and mixed signal design language VHDL-AMS, and derives general results about the behaviour of VHDL-AMS programs from it. We include, for example, a demonstration that VHDL-AMS parallelism is benign in the absence of shared initializations. As proof of concept we have built an interpreted simulator that prototypes the semantics and which runs multi-process mixed analog and digital descriptions correctly. Peter T. Breuer, Natividad Martínez Madrid, Jonathan P. Bowen, Robert B. France, María M. Larrondo-Petrie, Carlos Delgado Kloos |
DATE | 1 |
| 1997 | A Refinement Calculus for the Synthesis of Verified Hardware Descriptions in VHDLabstractA formal refinement calculus targeted at system-level descriptions in the IEEE standard hardware description language VHDL is described here. Refinement can be used to develop hardware description code that is “correct by construction”. the calculus is closely related to a Hoare-style programming logic for VHDL and real-time systems in general. That logic and a semantics for a core subset of VHDL are described. The programming logic and the associated refinement calculus are shown to be complete. This means that if there is a code that can be shown to implement a given specification, then it will be derivable from the specification via the calculus. Peter T. Breuer, Carlos Delgado Kloos, Andrés Marín López, Natividad Martínez Madrid, Luis Sánchez-Fernández 0001 |
ACM Trans. Program. Lang. Syst. | 1 |
| 1995 | A Simple Denotational Semantics, Proof Theory and a Validation Condition Generator for Unit-Delay VHDL
Peter T. Breuer, Luis Sánchez-Fernández 0001, Carlos Delgado Kloos |
Formal Methods Syst. Des. | 1 |
| 1995 | A PREttier Compiler-Compiler: Generating Higher-order Parsers in CabstractAbstract Top‐down (LL) context‐sensitive parsers with integrated synthesis and use of attributes are easy to express in functional programming languages, but the elegant functional programming model can also serve as an exact prototype for a more efficient implementation of the technology in ANSI C. The result is a compiler‐compiler that takes unlimited lookahead and backtracking, the extended BNF notation, and parameterized grammars with (higher‐order) meta‐parameters to the world of C programming. This article reports on the utility in question three years after public release.Preccgenerates standard ANSI C and is ‘plug compatible’ withlex‐ generated lexical analyzers prepared for the UNIXyacccompiler‐compiler. In contrast toyacc, however, the generated code is modular, which allows parts of scripts to be compiled separately and linked together incrementally. The constructed code is relatively efficient, as is demonstrated by the example Occam parser treated in depth here, but the main advantages we claim are ease of use, separation of specification and implementation concerns, and maintainability. Peter T. Breuer, Jonathan P. Bowen |
Softw. Pract. Exp. | 1 |
| 1994 | Proving Hardware Designs
Peter T. Breuer, Luis Sánchez-Fernández 0001, Carlos Delgado Kloos |
ICLP | 1 |
| 1994 | A software maintenance management model based on queueing networksabstractAbstract A model of the software maintenance process within a medium‐sized organization is described. We set out both the abstract model and its implementation as part of a management tool, the Intelligent Software Maintenance Management System (ISMMS) prototype. The ISMMS provides a simulation environment for two sorts of management activities. In interactive mode, the characteristics of a particular set of maintenance tasks can be fed into the simulation, and decisions on the allocation of real personnel, tools and resources tested. In automatic mode, a spectrum of tasks is generated and different automatic allocation strategies are statistically evaluated against these. In both modes, the simulation draws on a database which is customized to accurately reflect the particular resources and characteristics of the organization using the model. The detailed abstract maintenance process underlying the prototype is described in terms of queues arranged in a topological network. This provides a clean conceptual model which has been successfully implemented using a three‐layer software architecture in the ISMMS prototype; the abstract queueing model is implemented as a synchronized predicate‐net which in turn is implemented in Prolog, and we describe the implementation here, as well as its behaviour from the user's point of view. Giorgos Papapanagiotakis, Peter T. Breuer |
J. Softw. Maintenance Res. Pract. | 2 |
| 1994 | Decompilation: The Enumeration of Types and GrammarsabstractWhile a compiler produces low-level object code from high-level source code, a decompiler produces high-level code from low-level code and has applications in the testing and validation of safety-critical software. The decompilation of an object code provides an independent demonstration of correctness that is hard to better for industrial purposes (an alternative is to prove the compiler correct). But, although compiler compilers are in common use in the software industry, a decompiler compiler is much more unusual. It turns out that a data type specification for a programming-language grammar can be remolded into a functional program that enumerates all of the abstract syntax trees of the grammar. This observation is the springboard for a general method for compiling decompilers from the specifications of (nonoptimizing) compilers. This paper deals with methods and theory, together with an application of the technique. The correctness of a decompiler generated from a simple occam-like compiler specification is demonstrated. The basic problem of enumerating the syntax trees of grammars, and then stopping, is shown to have no recursive solution, but methods of abstract interpretation can be used to guarantee the adequacy and completeness of our technique in practical instances, including the decompiler for the language presented here. Peter T. Breuer, Jonathan P. Bowen |
ACM Trans. Program. Lang. Syst. | 1 |
| 1993 | Formal specifications in software maintenance: from code to Z++ and back again
Jonathan P. Bowen, Peter T. Breuer, Kevin Lano |
Inf. Softw. Technol. | 2 |
| 1993 | Reverse-engineering Cobol via formal methodsabstractAbstract We describe methods and software tools which aid in reverse‐engineering COBOL application programs back to specifications (and in validating them against specifications). The aim is to create object‐based abstractions from the implementation to capture design and functionality. The central process which the tools support is ‘transformation from formalism to formalism’, first from COBOL to the intermediate language Uniform, then from Uniform to a functional description language, and then to the specification language Z. In the process, dataflow diagrams, entity‐relationship diagrams and call‐graphs, and other types of information, are extracted from the code. Kevin Lano, Peter T. Breuer, Howard P. Haughton |
J. Softw. Maintenance Res. Pract. | 2 |
| 1991 | Creating specifications from code: Reverse-engineering techniquesabstractAbstract Reverse‐engineering application codes back to the design and specification stage may entail the recreation of lost information for an application, or the extraction of new information. We describe techniques which produce abstractions in object‐oriented and functional notations, thus aiding the comprehension of the essential structure and operations of the application, and providing formal design information which may make the code much more maintainable and certainly more respectable. The two types of application considered here are (1) data processing applications written in COBOL — of primary importance owing to their predominance in present computing practice — and (2) scientific applications written in FORTRAN. These two require somewhat different abstraction approaches. Peter T. Breuer, Kevin Lano |
J. Softw. Maintenance Res. Pract. | 1 |