Memristors, traditionally considered as non-volatile resistive memories for high-density applications, also exhibit excellent sensitivity to chemicals, making them suitable for chemical sensing with intrinsic memory capabilities. This paper introduces an innovative technique for directly measuring and digitising sensor readings, such as gas concentration, using the switching state of the device, which is influenced by the applied bias voltage or current in the presence of chemicals. When a sensor itself detects and measures a chemical property, its state changes, enabling the direct digitisation of the sensed information. The proposed memristive sensor employs a TiO 2 based memristor as both the sensing and digitising element, and is evaluated using SPICE simulations with hydrogen gas (H 2 ) at different concentrations. We present a calibration curve that establishes a reliable correlation between pulse counts and chemical concentration, highlighting the consistent relationship between switching behaviour and concentration levels. This method significantly reduces the reliance on separate analogue to digital converters (ADC), simplifying the sensor architecture in terms of power consumption and circuit complexity. Additionally, the inherent nonlinearity of the fabricated devices renders this digitisation method significantly nonlinear, which can provide an added layer of security to the measured information. This approach paves the way for compact, low-power chemical sensing nodes, making them suitable for future integrated environmental monitoring systems.

This paper evaluates the yield of a memristor-based crossbar array of artificial neural networks in the presence of stuck-at-faults (SAFs). A technique based on Markov chains is used to estimate the yield in the presence of stuck-at-faults. This method provides a high degree of accuracy. Another method that is used for analysis and comparison is the Poisson distribution, which uses the sum of all repairable fault patterns. A fault repair mechanism is also considered when evaluating the yield of the memristor crossbar array. The results demonstrate that the yield could be improved with redundancies and a higher repairable stuck-at-fault ratio.

We propose novel memristive gas sensor architectures that can significantly reduce process and parametric variations in a predictable manner, while improving accuracy and overall power consumption. The proposed architecture can also be configured to realize multifunction logic operations as well as Complementary Resistive Switch with low hardware overhead in the absence of gasses. Our results show that the proposed architecture is significantly immune to process and parametric effects compared to a single sensor and almost unaffected by wire resistance, while offering much higher accuracy and much lower power consumption compared to existing techniques.

This paper proposes a method to calculate the yield of a memristor based sensor array considered as the probability that the chip provides acceptable sensing results when the array is affected by manufacturing defects. The modeling is based on a Markov Chain approach, in which each state represents an operating chip configuration and the state transitions take into account manufacturing defects. The proposed method is applicable to evaluate the yield with different fault models to achieve the comparative yield obtained by several redundancy allocations.

Memristors are an attractive option for use in future architectures due to their non-volatility, high density and low power operation. Gas sensing is one of the proposed application of memristive devices. In spite of these advantages, memristors are susceptible to defect densities due to the nondeterministic nature of nano-scale fabrication. In this paper, a novel spice memristor model incorporating fault models that emulates the gas sensing behaviour with/without faults is developed for simulation and integration with design automation tools. Our simulation results show that the proposed non-linear model detects the presence of the oxidising/reducing gas and analyses the defects/faults affecting the functionality of the sensor.

Resistive memory, also known as memristor, is an emerging potential successor to traditional CMOS charge based memories. Memristors have also recently been proposed as a promising candidate for several additional applications such as logic design, sensing, non-volatile storage, neuromorphic computing, Physically Unclonable Functions (PUFs), Content-addressable memory (CAM) and reconfigurable computing. In this paper, we explore three unique applications of memristor technology based implementations, specifically from the perspective of sensing, logic, in-memory computing and their solutions. We review solar cell health monitoring and diagnosis, describe the proposed solutions, and provide directions in memristive gas sensing and in-memory computing. For the gas sensor application, in order to determine the number of memristors to ensure a certain level of accuracy in sensitivity, a technique to optimize the sensor array based on an acceptable sensitivity variation and minimum sensitivity margin is presented. These “out-of-the-box” emerging ideas for applications of memristive devices in enhancing robustness and, at the same time, how the requirements of robust design are enabling unconventional use of the devices. To this end, the papers considers some examples of this mutual interaction.

Gas sensing is one of the proposed application field of memristive devices. We used a crossbar array of memristors as gas sensor using the HP labs fabricated TiO2based memristor model in an attempt to improve sensing accuracy. We introduced the possibility of reliable multiple gases detection using multiple rows of memristors as separate sensor in a crossbar array. Our experimental results show that an array of memristors can minimise measurement errors as well as provide a good redundancy measure during gas sensing. Measurements taken from the sensors are also not affected by alternate current paths problem often experienced in crossbar architecture.

Resistive memories have simpler structures and are capable of producing highly dense memory through crossbar architecture without the use of access devices. Reliability however remains a problem of resistive memories especially in its basic read operation. This paper presents a comprehensive model for resistive devices in crossbar array as well as models for four crossbar read schemes. These models are non-restrictive and are suitable for accurate analytical analysis of crossbar arrays and the evaluation of their performance during read operation.

This paper presents a novel low-complexity cross parity code, with a wide range of multiple bit error correction capability at a lower overhead, for improving the reliability in circuits over GF(2m). For an m input circuit, the proposed scheme can correct m ≤ Dw≤ 3m/2-1 multiple error combinations out of all the possible 2m- 1 errors, which is superior to many existing approaches. From the mathematical and practical evaluations, the best case error correction is m/2 bit errors. Tests on 80-bit parallel and, for the first time, on 163-bit Federal Information Processing Standard/National Institute of Standards and Technology (FIPS/NIST) standard word-level Galois field (GF) multipliers, suggest that it requires only 106% and 170% area overheads, respectively, which is lower than the existing approaches, while error injection-based behavioral analysis demonstrates its wider error correction capability.

Concurrent error detection and correction is an effective way to mitigate fault attacks in cryptographic hardware. Recent work on differential power analysis shows that even mathematically-secure cryptographic protocols may be vulnerable at the physical implementation level. By measuring energy consumed by a working digital circuit, it is possible to gain valuable information about the encryption algorithms used and even the specific encryption keys. Thwarting such attacks requires a new approach to logic and physical designs. This paper presents a systematic approach to fault tolerant cryptographic hardware designs. Firstly, the effectiveness of the Hamming code based error correction schemes as a fault tolerance method in stream ciphers is investigated. Coding is applied to Linear Feedback Shift Registers (LFSR) based stream cipher implementations. The method was implemented on industrial standard stream ciphers, e.g. A5/1(GSM), E0 (Bluetooth), RC4 (WEP), and W7. The performance variation of stream cipher algorithms with error detection and correction was studied by synthesising the designs on Field Programmable Logic Arrays (FPGA) and Application Specific Integrated Circuits (ASIC). Further, we analyse hardware building blocks to minimise switching activity of a circuit over all possible inputs and input transitions by adding redundant gates and increasing the overall number of signal transitions. We also discuss the overhead and compositional properties of uniformly-switching circuits.

We propose a C-testable S-box implementation which is one of the most complex blocks in AES hardware implementation. Only 12 constant vectors are sufficient to achieve 100% fault coverage in the S-box. C-testability is achieved with an extra hardware overhead of 8.2 percent.

Error correction is an effective way to mitigate fault attacks in cryptographic hardware. It is also an effective solution to soft errors in deep sub-micron technologies. To this end, we present a systematic method for designing single error correcting (SEC) and double error detecting (DED) finite field (Galoisfield) multipliers over GF(2m). The detection and correction are done on-line. We use multiple Parity Predictions (PPs) to correct single errors based on the Hamming principles. Specifically, a structural approach is first presented. The predicted parities are derived from the input operands. Further, a hybrid approach is presented where the multipliers and PP circuits are synthesized, and the decoding and correction circuits are structurally combined to form the complete error correcting designs. Our technique, when compared with existing techniques, gives better performance. We show that our SEC multipliers over GF(2m) require about 100% extra hardware, whereas with the traditional SEC techniques, such as the triple-modular redundancy (TMR), this figure is more than 200%.

Motivated by the problems associated with soft errors in digital circuits and fault related attacks in cryptographic hardware, we presented a systematic method for designing single error correcting multiplier circuits for finite fields or Galois fields over GF(2m) in [7]. We used multiple parity predictions to correct single errors based on the Hamming principles. The problem with Hamming based error correction is the delay overhead. To mitigate the delay overhead, in this paper we present single error correction using Low Density Parity Check Codes (LDPC). The expressions for the parity prediction are derived from the input operands, and are based on the primitive polynomials of the fields. Our technique, when compared with existing techniques, gives better performance. We show that our Single Error Correction (SEC) multipliers over GF(2m) require slightly over 100 percent extra hardware, whereas with the traditional SEC techniques this figure is more than 200 percent.

This paper presents an algebraic testing method for detecting stuck-at faults in the polynomial-basis (PB) bit-parallel (BP) multiplier circuits over GF(2m). The proposed technique derives the test vectors from the expressions of the inner product (IP) variables without any requirement of the ATPG tool. This low- complexity testing method requires (2m + 1) test vectors for detecting single stuck-at faults in the AND part and multiple stuck-at faults in the EXOR part of the multiplier circuits. The test vectors are independent of the multiplier's structure, as proposed in (T. A. Gulliver et al., 1991), but are dependent on m. For the multiplier circuits, the test set is found to be smaller in size than the ATPG-generated test set. The test set provides 100 percent single stuck-at fault coverage.

This paper presents an efficient technique for synthesis and optimization of the polynomials over GF(2m), where to is a nonzero positive integer. The technique is based on a graph-based decomposition and factorization of the polynomials, followed by efficient network factorization and optimization. A technique for efficiently computing the coefficients of the polynomials over GF(pm), where p is a prime number, is first presented. The coefficients are stored as polynomial graphs over GF(pm). The synthesis and optimization is initiated from this graph-based representation. The technique has been applied to minimize multipliers over the fields GF(2k), where k = 2,...,8, generated with all the 51 primitive polynomials in the 0.18-mum CMOS technology with the help of the Synopsys design compiler. It has also been applied to minimize combinational exponentiation circuits, parallel integer adders and multipliers, and other multivariate bit- as well as word-level polynomials. The experimental results suggest that the proposed technique can reduce area, delay, and power by significant amounts. We also observed that the technique is capable of producing 100% testable circuits for stuck-at faults.

We present a C-testable design of polynomial basis (PB) bit-parallel (BP) multipliers over GF(2 m ) for 100% coverage of stuck-at faults. Our design method also includes the method for test vector generation, which is simple and efficient. C-testability is achieved with three control inputs and approximately 6% additional hardware. Only 8 constant vectors are required irrespective of the sizes of the fields and primitive polynomial. We also present a Built-In Self-Test (BIST) architecture for generating the test vectors efficiently, which eliminates the need for the extra control inputs. Since these circuits have critical applications as parts of cryptography (e.g., Elliptic Curve Crypto (ECC) systems) hardware, the BIST architecture may provide with added level of security, as the tests would be done internally and without the requirement of probing by external testing equipment. Finally we present experimental results comprising the area, delay and power of the testable multipliers of various sizes with the help of the Synopsys® tools using UMC 0.18 micron CMOS technology library.

This paper presents the generalized theory and an efficient graph-based technique for the calculation and representation of coefficients of multivariate canonic polynomials over arbitrary finite fields in any polarity. The technique presented for computing coefficients is unlike polynomial interpolation or matrix-based techniques and takes into consideration efficient graph-based forms which can be available as an existing resource during synthesis, verification, or simulation of digital systems. Techniques for optimization of the graph-based forms for representing the coefficients are also presented. The efficiency of the algorithm increases for larger fields. As a test case, the proposed technique has been applied to benchmark circuits over GF(2m). The experimental results show that the proposed technique can significantly speed up execution time.

This paper presents a technique for representing multiple-output binary and word-level functions in GF(JV) (where N = pm, p is a prime number, and m is a nonzero positive integer) based on decision diagrams (DDs). The presented DD is canonical and can be made minimal with respect to a given variable order. The DD has been tested on benchmarks, including integer multiplier circuits, and the results show that it can produce better node compression (more than an order of magnitude in some cases) compared to shared binary DDs (BDDs). The benchmark results also reflect the effect of varying the input and output field sizes on the number of nodes. Methods of graph-based representation of characteristic and encoded characteristic functions in GF(iV) are also presented. Performance of the proposed representations has been studied in terms of average path lengths and the actual evaluation times with 50,000 randomly generated patterns on many benchmark circuits. All of these results reflect that the proposed technique can outperform existing techniques.

This paper presents an efficient technique for synthesis and optimization of polynomials over GF(2m), where m is a non-zero positive integer. The technique is based on a graph-based decomposition and factorization of polynomials over GF(2m), followed by efficient network factorization and optimization. A technique for efficiently computing coefficients over GF(pm), where p is a prime number, is first presented. The coefficients are stored as polynomial graphs over GF(pm). The synthesis and optimization is initiated from this graph based representation. The technique has been applied to minimize multipliers over all the 51 fields in GF(2k), k = 2...8 in 0.18 micron CMOS technology with the help of the Synopsys® design compiler. It has also been applied to minimize combinational exponentiation circuits, and other multivariate bit- as well as word-level polynomials. The experimental results suggest that the proposed technique can reduce area, delay, and power by significant amount.

This paper presents a new decision diagram (DD), called MODD, for multiple output binary and multiple-valued functions. This DD is canonic and can be made minimal with respect to a given variable order. Unlike other reported DDs, our approach can represent arbitrary combination of bits at the word-level. The preliminary results show that our representation can result in considerable memory saving.