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V. Lebars

dblp:14/5598 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 2005
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Integrated circuit design · 100%
Computer networks
1 paper
Physical-layer communications · 100%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Integrated circuit design
digital circuit design		 0.112005
A 135Mbps DVB-S2 compliant codec based on 64800-bit LDPC and BCH codes (ISSCC paper 24.3) · DAC 2005
Physical-layer communications › channel coding › error control coding › block codes
BCH codes		 0.012005
A 135Mbps DVB-S2 compliant codec based on 64800-bit LDPC and BCH codes (ISSCC paper 24.3) · DAC 2005
Physical-layer communications
channel coding		 0.012005
A 135Mbps DVB-S2 compliant codec based on 64800-bit LDPC and BCH codes (ISSCC paper 24.3) · DAC 2005
Physical-layer communications › channel coding › error control coding › block codes
LDPC codes		 0.012005
A 135Mbps DVB-S2 compliant codec based on 64800-bit LDPC and BCH codes (ISSCC paper 24.3) · DAC 2005

Methods — techniques the papers use, named apart from their topics

low-leakage CMOS design · 0.1
YearPublicationVenuePosition
2005 A 135Mbps DVB-S2 compliant codec based on 64800-bit LDPC and BCH codes (ISSCC paper 24.3)
abstract
A DVB-S2 compliant codec is implemented in both 130nm-8M and 90nm-7M low-leakage CMOS technologies. The system includes encoders and decoders for both Low-Density Parity Check (LDPC) codes and serially concatenated BCH codes. All requirements of the DVB-S2 standard are supported including code rates between 1/4 and 9/10, block sizes of either 16,200 bits or 64,800 bits, and four digital modulation options. The 130nm core design occupies 49.6mm2 and operates at 200MHz, while the 90nm core design occupies 15.8mm2 and operates at 300MHz.
Pascal Urard, L. Paumier, P. Georgelin, T. Michel, V. Lebars, E. Yeo
 DAC5