Data center operators are increasingly focusing on disaggregated computing to enhance resource utilization efficiency by pooling and logically connecting resources such as CPUs, memories, and accelerators. In disaggregated computing, data transfer between resources is fundamental for service execution. Conventional CPU-mediated data transfer often leads to communication bottlenecks due to data concentration. Therefore, direct data communication between heterogeneous computational resources is critical. To efficiently execute services through direct communication between heterogeneous computational resources, efficient allocation of computational resources and determination of routing paths should be done before service execution. In this paper, we propose a resource allocation method that effectively utilizes heterogeneous computational resources in disaggregated computing by modeling the impact of the characteristics of heterogeneous computational resources and parallel processing. Our method can derive the solution of this model in a practical amount of time. Simulation results show that the proposed method could decrease the number of resources by an average of 28% to 51% compared to the conventional method in a heterogeneous disaggregated computing system while meeting the service performance requirements.

In this paper, we assume an error such that a single insertion occurs and then a single deletion occurs. Under such an error model, this paper provides a decoding algorithm for non-binary quantum codes constructed by Matsumoto and Hagiwara.

This paper describes a real-time 4K/60p High Efficiency Video Coding (HEVC, the latest coding standard) multi-bitrate encoding system with content-aware bitrate control. Our encoding system has multiple encoding core LSIs that can each encode 4K/60p or up to HD x 4 streams. To reduce streaming bandwidth consumption, the encoding channels adopt dynamic seamless bitrate control, which is based on content aware bitrate control and supports multi- channel real-time encoding for adaptive bitrate streaming. Experimental results show the system reduces bitrates obtained with constant bitrate encoding by as much as 56.7%.

High frame rate (HFR) video is attracting strong interest since it is considered as a next step toward providing Ultra-High Definition video service. For instance, the Association of Radio Industries and Businesses (ARIB) standard, the latest broadcasting standard in Japan, defines a 120 fps broadcasting format. The standard stipulates temporally scalable coding and hierarchical transmission by MPEG Media Transport (MMT), in which the base layer and the enhancement layer are transmitted over different paths for flexible distribution. We have developed the first ever MMT transmitter/receiver module for 4K/120fps temporally scalable video. The module is equipped with a newly proposed encapsulation method of temporally scalable bitstreams with correct boundaries. It is also designed to be tolerant to severe network constraints, including packet loss, arrival timing offset, and delay jitter. We conducted a hierarchical transmission experiment for 4K/120fps temporally scalable video. The experiment demonstrated that the MMT module was successfully fabricated and capable of dealing with severe network constraints. Consequently, the module has excellent potential as a means to support HFR video distribution in various network situations.

This paper describes a motion estimation (ME) engine that achieves both power efficiency and coding quality for real-time ultra-high definition video encoders. Sum of absolute difference (SAD) calculations are performed with bit-shortened SAD engines to reduce power, and bit extraction positions are adaptively shifted in accordance with the flatness of picture luminance values to maintain calculation precision. Power simulations with a High Efficiency Video Coding encoder LSI design [2] show that the ME engine reduces power consumption by 18-39% with 4-bit shortened SAD calculation, while coding efficiency loss is suppressed by up to 57% with adaptive bit-shifting. The ME engine is especially effective for high dynamic range pictures with downscaled luminance values, which are suitable for today's 4K and 8K video contents.

This paper proposes a new architecture for VASA, a single-chip MPEG-2 422P@HL CODEC LSI with multichip configuration for large scale processing beyond the HDTV level, and demonstrates its flexibility and usefulness. VASA is the world's first single-chip full-specs MPEG-2 422P@HL CODEC LSI with a multichip configuration. An LSI was successfully fabricated using the 0.13-mum eight-metal CMOS process. The architecture not only provides an MPEG-2 422P@HL CODEC but also large scale processing beyond the HDTV level for digital cinema and multiview/-angled live TV applications with a multichip configuration. The VASA implementations will lead to a new dimension in future high-quality, high-resolution digital multimedia entertainment.