The introduction of general-purpose microprocessors running multiple threads will put a focus on methods and tools helping a programmer to write efficient parallel applications. Such a tool should be fast enough to meet a software developer's need for short turn-around time, but also be accurate and flexible enough to provide trend-correct and intuitive feedback. This paper presents a novel sample-based method for analyzing the data locality of a multithreaded application. Very sparse data is collected during a single execution of the studied application. The architectural-independent information collected during the execution is fed to a mathematical memory-system model for predicting the cache miss ratio. The sparse data can be used to characterize the application's data locality with respect to almost any possible memory system, such as complicated multiprocessor multilevel cache hierarchies. Any combination of cache size, cache-line size and degree of sharing can be modeled. Each modeled design point takes only a fraction of a second to evaluate, even though the application from which the sampled data was collected may have executed for hours. This makes the tool not just usable for software developers, but also for hardware developers who need to evaluate a huge memory-system design space. The accuracy of the method is evaluated using a large number of commercial and technical multi-threaded applications. The result produced by the algorithm is shown to be consistent with results from a traditional (and much slower) architecture simulation.

Performance tools based on hardware counters can efficiently profile the cache behavior of an application and help software developers improve its cache utilization. Simulator-based tools can potentially provide more insights and flexibility and model many different cache configurations, but have the drawback of large run-time overhead.We present StatCache, a performance tool based on a statistical cache model. It has a small run-time overhead while providing much of the flexibility of simulator-based tools. A monitor process running in the background collects sparse memory access statistics about the analyzed application running natively on a host computer. Generic locality information is derived and presented in a code-centric and/or data-centric view.We evaluate the accuracy and performance of the tool using ten SPEC CPU2000 benchmarks. We also exemplify how the flexibility of the tool can be used to better understand the characteristics of cache-related performance problems.

The widening memory gap reduces performance of applications with poor data locality. Therefore, there is a need for methods to analyze data locality and help application optimization. In this paper we present StatCache, a novel sampling-based method for performing data-locality analysis on realistic workloads. StatCache is based on a probabilistic model of the cache, rather than a functional cache simulator. It uses statistics from a single run to accurately estimate miss ratios of fully-associative caches of arbitrary sizes and generate working-set graphs. We evaluate StatCache using the SPEC CPU2000 benchmarks and show that StatCache gives accurate results with a sampling rate as low as 10/sup -4/. We also provide a proof-of-concept implementation, and discuss potentially very fast implementation alternatives.

This paper reports on the development of a flexible 5-MBd equalized M-QAM testbed for high-speed wireless data communications. The unit operates in real time and was field tested in typical indoor environments. A total of 3600 independent experiments were conducted using the testbed where one of 4-, 16-, 64-QAM constellations were transmitted, and the performance as a function of adaptive equalization and antenna selection diversity was studied. The experimental results presented here help put previous simulation and analytical results into perspective and demonstrate some of the performance bounds associated with a practical implementation. The field trial results show that with only 10-mW of transmit power, reliable 10-Mbit/s data communication can take place in between rooms with a coverage radius of 17 m, and better than 15% outage at an uncoded bit error rate (BER) of 10/sup -3/. The addition of two-branch antenna selection diversity to the system would allow 10-Mbit/s transmission at better than 3% outage and 20-Mbit/s transmission at 10% outage in the same environment. Moreover, 30-Mbit/s data transmission is feasible when both the transmitter and receiver are located within the same room, albeit at higher outage levels. In general, the results demonstrate the tremendous impact that adaptive equalization can have on the achievable performance of indoor links. Average SNR was improved anywhere from 8 dB to 12 dB depending on the particular environment and data rate. The impact on the outage performance, however, was much more dramatic.