This work presents a single-stage operational transconductance amplifier (OTA) with high DC gain for driving nano-farad capacitive loads. The circuit employs two conjugated current mirrors to form high-impedance nodes, enhancing transconductance and driving capability. Flipped-voltage follower (FVF) cells act as variable tail current sources to boost transconductance and generate a dynamic current larger than the bias current during slewing, enabling a faster transient response. The FVFs also allow additional folded drivers on the cascode stage for further improvement. To integrate these techniques, both n- and p-channel differential pairs are used at the input. Implemented in TSMC 0.18-μm CMOS, the OTA achieved a simulated DC gain above 100 dB and a measured gain of 95 dB, validating the proposed design. It shows a unity-gain bandwidth of 5.85 MHz and a slew rate of 0.347 V/μs while driving a 2×4 nF load at 1.8 V.

The large number of parameters in DNNs poses significant challenges for resource-constrained hardware. To address this, researchers have focused on model sparsity to skip redundant computations and improve inference speed and computing-in-memory (CIM) techniques to reduce data transfer delays and lower energy consumption. However, leveraging activation sparsity within CIM macros remains challenging due to its architectural limitations, leading to bottlenecks in this research direction. This study proposes a activation compression method based on the CIM structure and weight sparsity, along with a new approach called sparse reciprocity, to enhance model sparsity. A high-area-efficiency CIM-based accelerator chip was developed using these techniques and prior expertise. Experiments on various models and data precisions demonstrate a activation compression ratio of up to 54%, with the proposed accelerator achieving an area efficiency of 243 GOPS/mm² for the VGG16 model and 363 GOPS/mm² for the ResNet18 model.

This work presents an ultralow-voltage and ultralow-power current-mode delta-sigma modulator designed for biomedical applications. To implement both the integrator and quantizer of the modulator, a bulk-driven current conveyor circuit is introduced. By satisfying the Barkhausen criterion, the proposed modulator can intrinsically oscillate, producing a pulse-density modulated (PDM) output. This clock-less operation avoids conventional quantization noise associated with discrete-time sampling. The current-mode design not only provides improved matching properties and a wider bandwidth but also simplifies the implementation of passive components, resulting in a smaller silicon area compared to voltage-mode modulators—though this area efficiency is partly achieved using off-chip components. The circuit has been fabricated using standard TSMC 0.18-$\mu $m CMOS technology, occupying a silicon area of$226~\mu $m×$264~\mu $m. Despite consuming only 34 nW of power, experimental results demonstrate a signal-to-noise and distortion ratio of 57.1 dB, corresponding to an effective resolution of 9.2bits with a bandwidth of 81 Hz. Additionally, the use of the bulk-driven method achieves an input dynamic range of ±24nA under a supply voltage of 0.3 V.

In this paper, a power-efficient low-noise LFP/AP recording analog front end with real-time stimulation artifact removal is proposed. During closed-loop stimulations, the artifact removal is realized through AB-IPC (Artifact Blanking Input Protection Circuit) by blanking the front end with a clock synchronized to the stimulation-enable signal. After stimulation, the proposed front-end can quickly recover back to recording mode. Furthermore, to prevent amplifier saturation due to sudden signals, we have utilized an adjustable gain design, including modes with 45, 50, and 60dB selection. In terms of adjustable bandwidth, the high-pass corner frequency ranges from 0.614 - 300Hz, and the low-pass corner frequency is 6.7kHz. Through chopping stabilization techniques, input equivalent noise reaches 0.89uVrms in the 0.5Hz-300Hz and 2.55uVrms in the 300-5kHz frequency bands, while power consumption remains within the range of 3.95uW. It is shown that the proposed AFE acquisition circuit is suitable for implantable closed-loop DBS (Deep Brain Stimulation) control systems.

Convolutional neural networks (CNNs) play a key role in many deep learning applications; however, these networks are resource-intensive. The parallel computing ability of computing-in-memory (CIM) enables high energy efficiency in artificial intelligence accelerators. When implementing a CNN in CIM, quantization and pruning are indispensable for reducing the calculation complexity and improving the efficiency of hardware calculations. Mixed-precision quantization with flexible bit widths provides a better efficiency-accuracy trade-off than fixed-precision quantization. However, CIM calculations for mixed-precision models are inefficient because the fixed capacity of CIM macros is redundant for hybrid precision distributions. To address this, we propose a software and hardware co-design SRAM-based CIM architecture called SUN, including a CIM-adaptive mixed precision joint pruning quantization algorithm and dynamic hybrid precision CNN accelerator. Three techniques are implemented in this architecture: (1) a mixed precision joint pruning algorithm for reducing the memory access and removing the redundant computing, (2) a CIM-adaptive filter-wise and paired mixed-precision quantization for improving CIM macro utilization, and (3) an SRAM-based CIM CNN accelerator in which the SRAM CIM macro is used as the processing element to support sparse and mixed-precision CNN computation with high CIM macro utilization. This architecture achieves a system area efficiency of 428.2 TOPS/mm2 and throughput of 792.2 GOPS on the CIFAR-10 dataset.

This paper presents a chopper-stabilized three-stage operational amplifier (OpAmp) with a unity gain bandwidth of 69 MHz and an input referred noise density of 3 nV$/\surd{Hz}$. The proposed design achieves a stable unity gain by proposing a new pole and zero scheme with very low power consumption, drawing only 3.3 mA from a 1.8 V power supply while driving a load capacitor as large as 100pF. To achieve rail-to-rail input swing, the design uses both NMOS and PMOS differential pairs at the input and biases them in the subthreshold region to provide an identical net trans-conductance over the rail-to-rail input common mode. Furthermore, an adaptive biasing is employed and the current sources are kept ON during large signal transitions at the input, thus eliminating crossover distortion and providing a high slew rate of 40 V/$\mu$s at a 100 pF load capacitor. The design employs chopping at 2.5 MHz and is enhanced with a local ripple reduction loop, making the OpAmp suitable for high gain and wide bandwidth applications with less filtering required. The design also reduces the input bias current significantly from 500 nA to 1.5 nA by buffering the input and applying it to the modified bootstrap switches. The proposed OpAmp, fabricated in a 0.18$\mu$m CMOS process, exhibits a maximum offset of 4.5$\mu$V, a flicker noise corner frequency of 246 Hz, a DC gain of 146 dB, a power supply rejection ratio of 123 dB, and a common mode rejection ratio of 116 dB.

This work presents a general enhancement in operational transconductance amplifiers (OTAs) by conjugating the diode-connected topologies of the current mirrors (CMs). The proposed conjugation method provides an internal high-impedance node, by which the transconductance of the amplifier is significantly increased. Since the central node of the conjugated CMs is virtually grounded for small differential signals, the cascode devices of the diode-connected topologies can be employed as an extra differential pair causing a further enhancement in transconductance. Moreover, the large signal behavior of the circuit shows that the conjugated CMs are capable of copying a dynamic current with a higher gain in comparison with a traditional CM amplifier. This advantage results in faster charging and discharging of the output capacitive load, which provides a larger slew rate (SR) without increasing the quiescent current. The proposed amplifier was manufactured with TSMC 0.18-$\mu $m CMOS technology occupying a silicon area of$55.5\times 48.9~\mu $m. Experimental results at a supply voltage of 1.8 V show a gain bandwidth (GBW) of 104.9 MHz, a dc gain of 79.1 dB, and an SR of 55.7 V/$\mu $s for a capacitive load of 10 pF, while the circuit consumes 489-$\mu $W power.

Conventional physics-based memristor device modeling methods highly rely on human expertise, which results in a long development period. To address the aforementioned challenges, we propose a new generalized memristor (GEM) device modeling framework based on the artificial neural network (ANN) technique, which has a minimum dependency on the underlying physics, resulting in a fast turn-around development time for customized memristor devices. GEM framework models the switching and conducting behaviors of the memristor devices separately, avoiding the signal-dependence issue in the prior time-series data modeling method. The result of the GEM framework is a compact model that supports general-purpose circuit simulators. Experimental results show that our compact model achieves a ratio of root-mean-square error to peak-to-peak (RMSE/PP) of 3.6% compared to the physics-based device model. Performance analysis of memristor-based logic and memristor crossbar circuits are conducted to demonstrate the effectiveness of our proposed GEM framework for the design and analysis of memristor-based circuits.

This brief implements a highly efficient fully differential transconductance amplifier, based on several input-to-output paths. Some traditional techniques, such as positive feedback, nonlinear tail current sources, and current mirror-based paths, are combined to increase the transconductance, thus leading to larger dc gain and higher gain bandwidth (GBW) product. Two flipped voltage-follower (FVF) cells are employed as variable current sources to provide class-AB operation and adaptive biasing of all other drivers. The proposed structure includes several input-to-output paths that play the role of dynamic current boosters during the slewing phase, thus improving the slew rate (SR) performance. The circuit was fabricated in a TSMC 0.18-$\mu \text{m}$CMOS process with a silicon area of$54.5\times 30.1\,\,\mu \text{m}$. Experimental results show a GBW of 173.3 MHz, a dc gain of 72.7 dB, and an SR of 139.4 V/$\mu \text{s}$for a capacitive load of$2\times5$pF. The proposed circuit consumes 619$\mu \text{W}$of power, under a supply voltage of 1.8 V.

In this brief, two current generator circuits are used to design a self-biasing transconductance amplifier. The current generators are configured using two n-channel and p-channel cascode current mirrors by which a high input dynamic range is achieved. Since such a topology creates positive feedback, the transconductance of the circuit is also increased causing higher performance. To ensure the stability of the circuit, constant current sources can be paralleled with the current mirror topologies, which of course are implemented using input drivers. Therefore, two n-channel and p-channel input differential pairs are added to the current generator circuits by which not only a rail-to-rail operation is achieved but also the amplifier is stabilized. The proposed circuit was fabricated in the TSMC 0.18-$\mu \text{m}$CMOS process with a silicon area of$54.1\times 71\,\,\mu \text{m}$. Under a 1.8-V supply voltage, the experimental results showed a high input common-mode range (ICMR), while a gain bandwidth (GBW) of 83.9 MHz was measured for a capacitive load of$2\times6$pF. In addition, a dc gain and a slew rate (SR) of 68.4 dB and 71.7 V/$\mu \text{s}$, respectively, were achieved.

The implementation of a power-efficient neuron array system with high throughput and controllable mismatch plays an important role in power-sensitive applications and brain simulations. This paper presents an array of 48 Integrate-and-Fire neurons with axon-sharing architecture implemented in 55-nm CMOS technology. The combination of log-domain circuits and comparator-sharing in neuron design achieves the integration of 3125 neurons/mm2and power consumption of 5.3 pJ/spike. The proposed time modulated axon-sharing synapse architecture realizes 5500 events/s/neuron unit throughput. A novel background calibration module is integrated to reduce the mismatch between neurons. Simulations presents a 45% improvement in SD of inter-spike interval variation. Finally, we validate the architecture by implementing a spiking neural network for solving a 3-stage Sudoku Puzzle. 100% success rate is obtained after calibration.

Convolutional neural networks (CNNs) play a key role in deep learning applications. However, the large storage overheads and the substantial computational cost of CNNs are problematic in hardware accelerators. Computing-in-memory (CIM) architecture has demonstrated great potential to effectively compute large-scale matrix–vector multiplication. However, the intensive multiply and accumulation (MAC) operations executed on CIM macros remain bottlenecks for further improvement of energy efficiency and throughput. To reduce computational costs, model compression is a widely studied method to shrink the model size. For implementation in a static random access memory (SRAM) CIM–based accelerator, the model compression algorithm must consider the hardware limitations of CIM macros. In this study, a software and hardware co-design approach is proposed to design MARS, a SRAM-based CIM (SRAM CIM)-based CNN accelerator that can utilize multiple SRAM CIM macros as processing units and support a sparse CNN, and an SRAM CIM-aware model compression algorithm that considers a CIM architecture to reduce the number of network parameters. With the proposed hardware software co-designed method, MARS can reach over 700 and 400 FPS for CIFAR-10 and CIFAR-100, respectively. In addition, MARS achieves 52.3 and 88.2 TOPs/W in VGG16 and ResNet18, respectively.

This work presents a tail-less fully differential bulk-driven transconductance amplifier without using a common-mode feedback (CMFB) circuit. The proposed amplifier employs two P-type and N-type current mirrors to form two self-biasing positive feedback loops resulting in a double transconductance. The bulk terminals of the P-type current mirrors are used as the input nodes to provide a high input dynamic range. The diode-connected topologies of the current mirrors adaptively bias other transistors to cover the lack of the CMFB circuit. To ensure stability, additional current sources are paralleled with the positive feedback structures. A high output voltage swing and a high DC gain are achieved by adding an adaptively biased common-source amplifier as the output stage leading to a class-AB operation. A large signal analysis, in weak inversion, is also done to mathematically describe both small- and large-signal characteristics. The proposed circuit was fabricated using TSMC$0.18 \mu \text{m}$CMOS technology occupying a silicon area of$113\,\,\mu \text{m}\,\,\times 70\,\,\mu \text{m}$. Experimental results at a supply voltage of 0.4 V show a gain bandwidth of 7 kHz, a DC gain of 60 dB, and a slew rate of 79 V/ms with just 24 nW power dissipation while driving a capacitive load of$2\times 15$pF.

This article presents the experimental results for a multiple-input operational transconductance amplifier (MI-OTA). To achieve extended linearity under 0.5-V low voltage supply, the circuit employs three linearization techniques: the bulk-driven (BD), the source degeneration, and the input voltage attenuation created by the MI metal-oxide-semiconductor transistor technique (MI-MOST). Although the linearization techniques result in reduced dc gain, the self-cascode transistors are used to boost the gain of the MI-OTA. Furthermore, the MI-MOST simplifies the internal structure of the OTA and may reduce the complexity of the applications. The MI-OTA operates in the subthreshold region and offers tunability by a bias current in the nanoampere range. The circuit is capable to work with 0.5-V supply voltage while consuming 24.77 nW. The circuit was fabricated using the 0.18-$\mu \text{m}$Taiwan Semiconductor Manufacturing Company (TSMC) CMOS technology and it occupies a 0.01153-mm2 silicon area. Intensive simulation and experimental results confirm the benefits and robustness of the design.

The inner operations of the human brain as a biological processing system remain largely a mystery. Inspired by the function of the human brain and based on the analysis of simple neural network systems in other species, such as Drosophila, neuromorphic computing systems have attracted considerable interest. In cellular-level connectomics research, we can identify the characteristics of biological neural network, called population, which constitute not only recurrent fully- connection in network, also an external-stimulus and self- connection in each neuron. Relying on low data bandwidth of spike transmission in network and input data, Spiking Neural Networks exhibit low-latency and low-power design. In this study, we proposed a configurable population-based digital spiking neuromorphic processor in 180nm process technology with two configurable hierarchy populations. Also, these neurons in the processor can be configured as novel models, integer quadratic integrate-and-fire neuron models, which contain an unsigned 8-bit membrane potential value. The processor can implement intelligent decision making for avoidance in real-time. Moreover, the proposed approach enables the developments of biomimetic neuromorphic system and various low-power, and low-latency inference processing applications with normalized energy efficiency of 13.2 pJ/SOP.

This article presents a low-voltage high-transconductance input differential pair for bulk-driven amplifiers. The proposed structure employs two bulk-driven flipped voltage follower (FVF) cells as nonlinear tail current sources to enhance the slewing behavior. This method also increases the transconductance of the proposed amplifier two times against the conventional one. The enhanced topology is merged with a conventional bulk-driven input differential pair using cross-coupled connections to significantly increase the transconductance. These circuitry ideas lead to an improvement in the amplifier's specifications, such as dc gain, slew rate (SR), and input noise without any degeneration in other parameters. Moreover, thanks to the use of the bulk terminals as the input nodes and also a simple common-source structure as the second stage, rail-to-rail input, and output swings are achieved, respectively. The proposed amplifier was fabricated in TSMC 0.18- μm CMOS technology. Under a supply voltage of 0.5 V, the measurement results show that the proposed amplifier achieves a dc gain of 78 dB, a gain bandwidth of 7.5 kHz, and an SR of 8.6 V/ms with just 91-nA current dissipation.

This paper presents a batteryless DC-DC boost converter for thermoelectric energy harvesting application. With a stepping-up architecture and by inductor sharing, only one off-chip inductor is employed. Fabricated in 0.18μm CMOS process, the chip can be cold-started at 190mV and sustain operation with a minimum input voltage of 50mV. Zero-current switching (ZCS) and maximum power point tracking (MPPT) techniques are utilized to enhance the measured peak efficiency to 60%. And the output voltage can be regulated from 1V to 1.6V.

This paper describes a 10-bit successive approximation register (SAR) analog-to-digital converter (ADC) with an energy-efficient trilevel alternate switching capacitive digital-to-analog converter (CDAC). The switching scheme of this CDAC preserves the features of the asymmetric-switching CDAC. By narrowing and smoothing the dynamic variation of DAC voltage, the switching scheme diminishes the dynamic offset effect induced by the asymmetric-switching CDAC. The CDAC reduces the capacitor requirement by almost fourfold and improves the average switching energy efficiency by almost 86.5% when compared with the conventional switching CDACs. This SAR ADC was implemented using the 90-nm CMOS technology, and its measured performances were as follows: 1) spurious free dynamic range of 56.98 dB; 2) signal-to-noise-and-distortion ratio of 68.79 dB; and 3) power dissipation of 3.45 μW at an operation of 0.5 V and 1.28 MS/s. The ADC achieves a figure-of-merit of 4.68-fJ/conversion-step.

This paper presents a 10-bit successive approximation register (SAR) ADC with a detect logic for DAC switching. The proposed switching detect logic can avoid switch power wasted and reduce the impact of capacitor mismatch from the layout parasitic as well as improve the resolution performance of SAR ADC. The ADC consumes 3 uW at 0.5-V supply and 1.28-MS/s sampling rate, achieves high ENOB and FOM performance of 9.95-bit and 2.36 fJ/conversion-step, respectively. This SAR ADC is fabricated with the TSMC 90 nm CMOS process and occupies an active area of 238μm×200μm.

This paper serves as an introduction to visual prostheses. Visual prostheses have attracted a lot of attention in recent years. With the potential of helping the blind to regain or improve their vision, researchers have been trying to tap into the visual pathways using their novel circuits and systems and interact with the brain through electronic ways. Having already benefited a lot from recent advances in electronics, MEMS, materials, and other sciences and technologies, and having already achieved a lot in the past, research in this field still prompt researchers to go beyond what current technologies can offer. In particular, this paper will review the challenges associated with circuit design for the visual prostheses, for example, the high-voltage compliant circuits, high-density drivers, power management schemes, and efficient stimulation.

This paper presents a 10-bit successive approximation register (SAR) ADC with an energy-efficient switching approach of capacitive DAC. The proposed switching method lessens the dynamic offset effect coming from the asymmetric capacitive switching. A tri-level algorithm is applied additionally to make the ADC more power-efficient and is implemented with switching-capacitive voltage generator without consuming static power. It consumes 3.87μW at 0.5V supply and 1.28MS/s sampling rate, and achieves ENOB of 9.69-bit and FOM of 3.66 fJ/conversion-step. This SAR ADC has been fabricated by TSMC 90nm CMOS process technology.

This paper proposes a probabilistic spiking neural network (PSNN) with unimodal weight distribution, possessing long- and short-term plasticity. The proposed algorithm is derived by both the arithmetic gradient decent calculation and bioinspired algorithms. The algorithm is benchmarked by the Iris and Wisconsin breast cancer (WBC) data sets. The network features fast convergence speed and high accuracy. In the experiment, the PSNN took not more than 40 epochs for convergence. The average testing accuracy for Iris and WBC data is 96.7% and 97.2%, respectively. To test the usefulness of the PSNN to real world application, the PSNN was also tested with the odor data, which was collected by our self-developed electronic nose (e-nose). Compared with the algorithm (K-nearest neighbor) that has the highest classification accuracy in the e-nose for the same odor data, the classification accuracy of the PSNN is only 1.3% less but the memory requirement can be reduced at least 40%. All the experiments suggest that the PSNN is hardware friendly. First, it requires only nine-bits weight resolution for training and testing. Second, the PSNN can learn complex data sets with a little number of neurons that in turn reduce the cost of VLSI implementation. In addition, the algorithm is insensitive to synaptic noise and the parameter variation induced by the VLSI fabrication. Therefore, the algorithm can be implemented by either software or hardware, making it suitable for wider application.

This paper presents a low-power, neuromorphic spiking neural network (SNN) chip that can be integrated in an electronic nose system to classify odor. The proposed SNN takes advantage of sub-threshold oscillation and onset-latency representation to reduce power consumption and chip area, providing a more distinct output for each odor input. The synaptic weights between the mitral and cortical cells are modified according to an spike-timing-dependent plasticity learning rule. During the experiment, the odor data are sampled by a commercial electronic nose (Cyranose 320) and are normalized before training and testing to ensure that the classification result is only caused by learning. Measurement results show that the circuit only consumed an average power of approximately 3.6 μW with a 1-V power supply to discriminate odor data. The SNN has either a high or low output response for a given input odor, making it easy to determine whether the circuit has made the correct decision. The measurement result of the SNN chip and some well-known algorithms (support vector machine and the K-nearest neighbor program) is compared to demonstrate the classification performance of the proposed SNN chip.The mean testing accuracy is 87.59% for the data used in this paper.

This paper studies how the musical-rhythmic features affect the performance of heart rate variability (HRV). A physiological valence/arousal model of such a relationship is proposed. A systematic experiment was performed, subjecting human subjects to four different drum loops, in which was tried to define a set of rhythmic features (and 'factors') that could be correlated with the observed HRV readings. Twenty-two healthy subjects and these four testing rhythm patterns were studied in this paper. The results show that dedicated rhythm can be synthesized for relaxing and exciting, and such an understanding between music and autonomic nervous system can improve life and health by the next generation of biomedical entertainment platform.

The measurement of oxygen saturation using pulse oximeters requires clean photoplethysmograph (PPG) signals, as motion artifacts often lead to a significant degree of error in the computation. This paper proposes a method for reducing motion artifacts from corrupted PPG signals by applying a normalized least mean squares (NLMS) algorithm, using an isobestic point wavelength (800nm) as a noise reference signal for the adaptive filter. A finger ring type sensor was demonstrated to be more comfortable than a clip type sensor. Experimental results indicate that the proposed method is suitable for reconstructing PPG signals and improving the accuracy of measuring oxygen saturation in the blood.

This paper proposes a low-power, high-resolution Winner-Take-All (WTA) circuit basing on transistors in subthreshold operation. The WTA adapts a tree structure to reduce the effect of process variations. In addition to the traditional way of using positive feedback to improve the comparison performance, we propose to use translinear loop to amplify the difference between two inputs before comparison to achieve high resolution. The circuit has been fabricated with TSMC 0.35μm 2P4M process. The WTA operates with input current as low as a few nano amperes and resolution as high as 0.1%. Measurement results show that the circuit has a non-negligible offset. Discussions on the source of the offset with a proposed solution are also given.

The portable electronic nose system is composed of a sensor array (sensor head) part and an electronics part. The sensors are made of polymer/mesoporous carbon composite materials for high sensitivity and selectivity. The electronics are sensor interface circuitry together with a microprocessor.