In this paper, a rapid binary search-based calibration method for capacitor mismatch errors in CDAC structures is proposed. Limitations of existing methods, such as the need for ADC architecture modifications, long convergence times, and high design complexity, are addressed by this approach. By employing a simple binary search algorithm, capacitor weights are quickly optimized to maximize the SNDR, effectively calibrating capacitor mismatch errors. The implementation of this method is relatively straightforward, with comparatively low computational resource requirements, offering strong flexibility. Simulation results for a 14-bit Pipelined-SAR ADC model indicate that, after calibration, average SNDR and SFDR improvements of 8.74 dB and 20.65 dB, respectively, were achieved.

This article introduces a successive approximation register (SAR) analog-to-digital converter (ADC) that utilizes a foreground capacitor mismatch self-calibration method. The proposed floating operation puts the uncalibrated high-bit capacitor into the floating state, preventing the sub-ADC from saturating caused by comparator static offset during the calibration process. To address the random mismatch of the LSB capacitors and improve the calibration accuracy, this article employs round-robin grouping of eight sets of LSB capacitors. In addition, a precharged bootstrapped switch is proposed to achieve high sampling linearity with low power consumption and area overhead. An anti-interference custom-designed 0.5-fF capacitor structure is suggested for binary-weighted capacitor mismatch of capacitive DAC (CDAC). Furthermore, the circuit implementation of the comparator utilized by ADC is also discussed. The prototype was fabricated in a 180-nm CMOS process with a 1.8-V supply and achieved spurious-free dynamic ranges of 108.9 and 92.38 dB at an input frequency of 1 kHz while operating at sampling rates of 100 kS/s and 1 MS/s, respectively. The prototype consumes 6.745 mW and occupies 0.91$\text {mm}^{2}$.

This article presents a 1.5–4-GHz transmitter with a reconfigurable 10–200-MHz signal bandwidth, supporting multiband in 5G new radio (NR). A fully differential operational amplifier (OPA) with novel capacitor-coupled feedforward compensation is proposed to support broadband analog baseband (ABB) with enhanced efficiency and linearity. The linear-in-dB gain control method, utilizing the thermometer code and the reusable resistor block (RB), is proposed to ensure accurate and monotonic gain control. The proposed two-stage push–pull power driver amplifier (PDA), covering the 1.5–4-GHz range, employs an efficiency-enhanced on-chip transformer and switched-capacitor arrays to support broadband operation. Designed using a CMOS large-signal (LS) nonlinear model and the$\mathrm {G}_{\mathrm {3}}$fluctuation method, the complementary PDA extends the linear operating range, mitigates AM–PM distortion, and improves efficiency. Moreover, the matching network is systematically analyzed to achieve the most efficient power transfer and load matching. To compensate for the dc offset caused by process, voltage, and temperature (PVT) variations, as well as the dc level mismatch between ABB stages, both digital dc offset calibration circuits and an analog level shifter are integrated on-chip. The transmitter is implemented in 55-nm CMOS with a 1.8/2.5-V power supply and a core chip area of$\text {2.99 mm}^{2}$. The transmitter achieves S22 output matching below −12 dB across the 1.5–4-GHz frequency range and provides a 36-dB gain range with a 0.375-dB step. The measured error vector magnitude (EVM) for the NR40MHz signal is 1.67% at 4.2-dBm average output power in n41 and 1.54% at 3.7-dBm average output power in n78, with corresponding adjacent channel power ratio (ACPR) of −48.75 and −48.067 dBc, respectively.

This paper introduces a 0.5-V, two-stage, pseudo-differential bulk-driven operational transconductance amplifier with high gain and linearity for low-power continuous-time applications. The input stage’s common-mode feedback utilizes a linear resistor detector with a conductance reduction cross-coupled pair to mitigate the loading effect of the common-mode detector resistor at ultra-low power operations. Temperature dependence of the conductance reduction circuit is compensated. The impact of the conductance reduction circuit on linearity performance is explored. The output stage employs a class-AB topology and utilizes a phase lead compensator to stabilize the OTA. Implemented in 180 nm CMOS technology, this OTA achieves a DC gain and slew rate of 68 dB and 26.1 V/$\mu $s, respectively, under a capacitive load of 10 pF. The total power consumption is$34.2~\mu $W. With unit gain feedback configuration, the measured total harmonic distortion is only 0.02% at an output amplitude of 500 mVpp. Test results validate the proposed circuit, positioning it competitively compared to state-of-the-art designs.

The performance of zero intermediate frequency (IF) receiver is usually limited by the frequency dependent I/Q mismatch, which gets worse with the increase of the signal bandwidth. Because the frequency dependent errors caused by the mixer and the baseband filters are difficult to eliminate, digital calibration methods are widely adopted. Among all the calibration methods, the algorithm based on the detection in frequency domain is able to extract the error at different frequencies which makes it suitable for foreground calibration. This paper proposed a receiver I/Q mismatch calibration method applied to wideband FDD transceivers, which can extract the error in frequency domain by transmitting customized signals through transmitters. A reasonable frequency plan is adopted to avoid the interference of TX image, nonlinearity and LO leakage and the wideband I/Q mismatch is compensated by a complex finite impulse response (FIR) filter. The proposed algorithm fully utilizes the existing hardware of the receiver, achieving a good balance between algorithm performance and hardware cost, which is validated on a FDD transceiver platform and the image rejection ratio (IRR) is improved from 33dB to at least 66dB in the whole baseband with a bandwidth of 245MHz.

This paper presents a reconfigurable 4.75-to-32 GBuad transmitter (TX) that operates up to 64Gb/s with four-level pulse-amplitude modulation (PAM-4) and at 32Gb/s with non-return-to-zero (NRZ) modulation scheme, designed in the 28-nm CMOS technology. The TX incorporates a quarter-rate architecture with a tap coefficient flexible feed-forward equalizer (FFE) up to 3 FFE taps. The TX employs a tailless CML driver with common-mode feedback (CMFB) for output swing control which provides 0.8 V pp output swing, and a helical wiring T -coil for bandwidth expansion. The clock path of the TX includes the duty-cycle detection/correction (DCD/DCC) circuits with a resolution of sub-60fs and quadrature-error detection/correction (QED/QEC) circuits, and a LC phase locked loop (PLL) with a local injection-locked (IL) quadrature clock generation circuit. The TX operating at 64 Gb/s in PAM-4 modulation consumes 76.7 mW from 1-V supply with 0.8 V pp, achieving an 1.2 pJ/b energy efficiency. The TX front end occupies an active area of 0.063 mm2.

This paper presents a foreground calibration technique with LSB capacitors for an 18-bit SAR ADC. Calibration using LSB capacitors suffers from poor accuracy owing to the comparator static offset and the random mismatch in LSB capacitors. The proposed floating capacitors operation addresses the miscalibration due to the saturation of sub-ADC resulting from the static offset. In addition, calibration using multiple groups of LSB capacitors is taken for each capacitor measurement to average out the effect of random mismatch in LSB capacitors, which improves the calibration accuracy effectively. Behavioral simulations of an 18-bit SAR ADC demonstrate the availability and robustness of the proposed calibration techniques.

In this paper, a novel foreground calibration method for wideband zero IF receiver I/Q mismatch is proposed based on frequency domain feature extraction, which is suitable for the FDD transceiver integrated with digital signal processing modules. The proposed algorithm calibrates the frequency dependent mismatch through a complex digital FIR filter, and uses the transmitter as the signal source. A frequency allocation scheme is applied to avoid the interference from the transmitter image component. Mismatch factors such as LO phase and amplitude mismatch and baseband transfer function mismatch can be calibrated together directly by this method, which eliminates the error accumulation caused by multi-level cascade calibration. Finally, a high image rejection ratio is obtained, and the image component power is stably compressed below the quantization noise power in the whole baseband.

A 2.5 GS/s12-bit 4-channel time-interleaved SAR-assisted pipelined ADC is proposed. The bias-enhanced ring amplifier serves as a residual amplifier offering high bandwidth and superior power efficiency over conventional operational amplifier. A high linearity front-end is proposed to mitigate the non-linearity of the ESD diode and provide sufficient driving ability. In addition, it can reject the kickback noise from the core ADC. A digital background calibration method with digital-mixing is adopted to fix the mismatches among channels. The measured SNDR/SFDR with a low-frequency of the prototype ADC are 51.0/68.0 dB, achieving a competitive FoMwof 0.48 pJ/conv.-step at 2.5 GS/s.

This paper presents a single-coarse dual-fine architecture that improves energy-efficiency of pipelined-SAR analog-to-digital converters (ADCs). A coarse and fast sub-ADC is used to quantize the most significant bits (MSBs), which are encoded with a proposed residue transformation method to control the residue generation of the first stages in two fine channels. The residue voltages generate on the capacitive digital-to-analog converters (C-DACs) of split fine channels directly without successive approximation processes. Therefore, the conversion rate is increased and the power is reduced. A shuffle mechanism is introduced into split-ADC based digital background calibration to avoid the divergence of the conventional algorithm in the proposed architecture. A high-energy-efficiency dynamic amplifier is also introduced as the residue amplifier. A 14-bit 60-MS/s ADC is prototyped in a 28-nm CMOS process. The digital calibration engine operates under 0.9-V supply, other parts of the ADC core operate under 1.05-V supply. The ADC core consumes 4.26 mW. Measurement results show that the calibration improved the signal-to-noise and distortion ratio (SNDR) and spur-free dynamic range (SFDR) dramatically, the calibrated ADC achieves SNDR and SFDR of 66.9 dB and of 91.0 dB respectively, translating to a Schreier FoM of 165.4 dB and a Walden FoM of 39.3 fJ/conversion-step.

Parasitic attenuation, memory effect and channel-length modulation limit the linearity of the state-of-the-art CMOS integrated ADC input buffer, this paper introduces an operational amplifier assisted input buffer that improves the linearity. A bootstrapped switch with improved linearity is also presented. Simulation results show that the proposed input buffer achieves an averaged SFDR improvement of 15dB in the first Nyquist zone. The proposed bootstrapped switch achieves 8.8dB SFDR improvement near Nyquist input frequency compared to the conventional circuit. The proposed techniques improved the linearity of the sampling front-end significantly.

A SAR assisted pipeline ADC with an inter-stage ring amplifier is an energy efficient structure. The ring amplifier is an alternative to an OTA for its low power consumption and large output swing. To improve the accuracy of the common-mode feedback circuit and speed up the settling of the ring amplifier, an improved bias-enhanced ring amplifier is proposed. Additionally, to alleviate the loss of the ring amplifier's DC gain in the nanoscale CMOS process and to migrate the dynamic offset caused by the non-ideal switches, a gain error cancellation method is introduced by adding a feedforward amplification path. Designed in a 1 V 28 nm CMOS process, two cascaded pipeline stages and two time-interleaved SAR sub-ADCs make up the ADC. In the post layout simulation that includes transient noise and other non-ideal factors, this 12-bit ADC achieves 60.9dB SNDR and 72dB SFDR at a Nyquist input and sampled at 800 MS/s without analog cancellation, consuming 16.02mW. With gain error cancellation, SFDR is improved by more than 3dB.

A 100MS/s 12-bit SAR ADC designed for terahertz imaging sensor is presented. The proposed ADC utilizes coarse-fine SAR architecture to relax reference requirement and improve operation rate. Split-CDAC structure is applied to reduce chip area, and its LSBs capacitors are reused as a coarse DAC. Redundant capacitor arrays are applied in both coarse and fine ADCs. A power-and-area-efficient ADC with high sampling rate can be realized with these techniques combined. The prototype is implemented in TSMC 1P9M 65nm-CMOS process. The simulation result with noise and other on board non-ideal effects shows that the ADC consumes 1.8 mW with an SNDR 65.7 dB and an SFDR of 77.0 dB with a Nyquist input at 1.2V power supply, achieving an ENOB of 10.6-bit and a FoM of 11.6 fJ/conv-step.

This paper presents an 11bit 200MS/s SAR-assisted pipeline ADC with a 2.5bit front end stage and two time-interleaved 9bit sub-SAR ADCs, implemented in 65nm CMOS process. The bias-enhanced ring amplifier works as the residue amplifier for power efficiency and large signal swing. Two self-biased inverter stages are designed in the ring amplifier to maintain the closed loop stability. The SAR ADCs with custom capacitor arrays are featured by l.5bit acceleration in the second quantization step. With the least-mean-square algorithm calibration, this ADC achieves an ENOB of 9.5bit and a FoM of 15.7fJ/conv-step at a 2.4MHz input signal sampled at 200MHz.

Modern cloud storage requires a high throughput and low latency data protection system, which is usually implemented with an Advanced Encryption Standard (AES) hardware accelerator connected with CPU through PCI Express (PCIe). However, most existing systems cannot simultaneously achieve high throughput and low latency, as they impose conflicting requirements to the block size of packets used in PCIe. High throughput requires the block size to be larger, while low latency requires the block size to be smaller. To provide both high throughput and low latency, we have developed an FPGA based data protection system called sAES. It uses a highly pipelined Direct Memory Access (DMA) based PCIe interface. It can achieve 10.4 Gbps throughput when the block size is 512 bytes, which is 51 times higher than the state-of-the-art Speedy PCIe interface [1]. The worst latency of sAES is only 4.368 μs when its block size is 512 bytes.