This article presents a proposal for fault-tolerant task mapping on many-core processors to enhance system performance and reduce communication energy. The proposed algorithm maps tasks onto a 2-D mesh network-on-chip (NoC) and a modified NoC (MNoC) platform. The focus of this article is primarily on addressing permanent faults. In the scenario of a permanent fault within the mapped core, the algorithm also proposes a spare core placement strategy. This involves allocating the spare core based on considerations related to communication energy. The proposed task mapping algorithm underwent evaluation using various benchmarks, including multimedia and synthetic benchmarks. The results were then compared to those obtained from a 2-D mesh NoC and three related algorithms, all under the same task graph and NoC size. The simulation results showed that the proposed mapping algorithm on the modified NoC platform leads to improved performance and communication energy reductions when compared to the 2-D mesh NoC and the other three algorithms. To validate the proposed fault-tolerant task mapping algorithm on the modified NoC platform, A Field Programmable Gate Array (FPGA) was used to measure performance metrics such as application runtime, area, and on-chip power consumption in both faulty and non-faulty conditions. The hardware results indicated significant improvements when comparing the proposed FTTM on MNoC and 2-D NoC with existing approaches.

System-on-chip (SoC) has migrated from single core to multi core architectures to adapt the expanding intricacy of real time applications. Network-on-chip (NoC) is appeared as an alternative to deal with the communication issues in embedded system-on-chip architectures. In network-on-chip (NoC) design, application mapping plays a significant role. In this research paper, a modified 2-D mesh NoC architecture is introduced and proposed an effective mapping algorithm, which maps the cores in the modified NoC architecture based on a core efficient region (CER) to enhance the processor performance and reduces the communication energy. The outcomes of the simulation illustrate that the proposed strategy is outperformed comparing with the other mapping techniques in terms of communication energy and performance. Moreover, the proposed algorithm is relevant to both random and distributed core graphs.

With the large number of processors in the chip, the design of a well-organized communication framework is crucial to satisfy the energy and bandwidth of multi-core systems. Network-on-Chip (NoC) has become the standard communication outline to replace the bus networks. Wireless NoC is becoming well known to be an auspicious upcoming on-chip communication framework because of low latency and high bandwidth provided by this emerging technology. Mapping vertices on various cores of the network is a critical segment in Wireless NoC because it decides the communication energy and latency. To diminish the communication energy of application core graph on multi-processors architecture, we propose an efficient application core mapping algorithm for Wireless NoC, that maps the application cores on Wireless NoC platform based on preliminaries. Which has three key steps: finding the efficient mapping region, selecting the first vertex to be mapped and choosing the suitable core on the Wireless NoC platform. Our empirical evaluation shows that, the proposed efficient algorithm averagely reduces packet latency 12%, 18% and 25%, and communication energy 17%,23%,28% over the RRM [14], DAMA [13] and MCDM [11].

Network-on-Chips (NoCs) are suitable communication framework for on-chip multiprocessors. NoC performance parameters, such as execution time and energy consumption, affect overall processor performance. The execution time of NoC simulator mapping applications increases with the enhancement of the NoC size. To provide efficient mapping for performance improvement. In this paper, focus on an efficient mapping algorithm and applied machine learning techniques to predict the execution time and energy consumption of the mapped NoC. The experimental outcomes exhibit the proposed mapping algorithm can achieves approximately 80% and 75% accuracy for execution time and energy consumption prediction, respectively. This type of performance prediction can be constructive for ongoing processors.

Due to life style change, working habits and lack of physical activity many people are suffering from Diabetes and heart diseases. Diabetes is a chronic disease in which the glucose levels in human blood are more than the ideal levels. It is due to deficiency or insufficient insulin which is produced by beta cells in the pancreas. Insulin plays a key role in regulating excess glucose. However, excess glucose levels in the blood over a long period of time causes so many other complications like heard stroke, brain stroke, vision loss, etc. Heart disease is also an incessant disorder. It could be as devastating as possible. Hence, It is better to diagnosis these diseases in the early stages to prevent the loss. So, in this paper, we are proposing a 2-level ensemble framework by combining RBFN, PNN, SVM and logistic regression. The proposed model is validated using benchmark type-2 Diabetes data set called Pima Indian Diabetes data set and the statlog heart disease data set. The results are compared with state-of-the-art techniques in the literature and our proposed model outperforms in terms of accuracy, sensitivity and specificity.

This paper describes a novel SRAM architecture to improve read and write stability. Read stability is enhanced by increasing β ratio to 4 and write stability is enhanced by storage node charging and discharging through two transistors. The proposed 8T SRAM architecture is compared with Conventional 6T, decoupled 8T SRAM cell and 10T SRAM cell. 6T SRAM cell required 584.1mV word line voltage to write data into a cell at 1.2V supply voltage whereas the proposed SRAM cell requires only 512.8mV, leakage power is close to leakage power of 6T SRAM cell.

A fault aware core mapping on Network on Chip (NoC) requires an understanding the calculation of the functional metrics. The functional metrics are Node Average Distance (NAD), Placing unmapped Vertices Region (PVR) and Weighted Communication Energy(WCE). The traditional method of calculating functional metrics are using unmapped cores, distance and weight. However finding the exact values of the functional metrics is not always easy, particularly when busy cores and failed cores are mapped in the middle of available cores. This paper proposes an energy efficient fault aware core mapping algorithm that maps the cores onto the NoC under communication rate constraints to minimize the total communication energy using functional metrics. The simulation results show that proposed mapping algorithm has higher performance over BMAP, PMAP and NMAP algorithm present in literature by 25%, 42%, and 65% under single fault, 30%, 40%, and 60% under two faults and 40%, 44%, and 55% under four faults respectively.