The synthesis of distributed embedded systems by desynchronization starts from a synchronous model and keeps its functional behavior while generating a corresponding dataflow process network (DPN). This method supports the modeling of dynamic behaviors while avoiding the problems like deadlocks and buffer overflows in DPNs. However, a DPN can be heterogeneous in the sense that different nodes may exhibit either static or dynamic behaviors. An efficient synthesis method should automatically generate implementations by exploiting this heterogeneity.In this paper we improve the desynchronization process by exploiting synchronous components with various input/output behaviors which can then be desynchronized to a heterogeneous DPN where each node can be scheduled and executed accordingly. Moreover, a synthesis tool chain is developed to automatically synthesize the heterogeneous DPN to the open computing language (OpenCL) based implementation that can be deployed on various commercial off-the-shelf (COTS) target platforms.

The synthesis of distributed embedded systems from dataflow models like Kahn Process Networks (KPN) has to deal with particular problems like absence of deadlocks and buffer overflows. However, the verification of the absence of these problems for a KPN model is in general not decidable. Starting with synchronous models, desynchronization avoids such design difficulties by generating sound dataflow networks by correctness of construction. In this paper, we present a design flow following such an approach. Our design flow differs from previous work in the following aspects: The synchronous models are specified by an imperative synchronous language and are therefore better suited for control-intensive applications. Verification of desynchro-nization criteria is carried out efficiently with the help of model checking and SAT-solving, ensuring the compliance of the functional behavior. Qualified code is translated automatically into the KPN model. Finally, the KPN model is automatically synthesized to the open computing language (OpenCL) based implementation which is platform independent and can be executed on various commercial off-the-shelf target platforms.

The synthesis of distributed embedded systems based on desynchronization is attractive since it preserves the functional behavior of the synchronous model while avoiding the verification of the absence of problems like deadlocks and buffer overflows. In this paper, we improve the desynchronization process by introducing synchronous components with various input/output (IO) patterns which can then be desynchronized to a heterogeneous dataflow process network (DPN) where each node can be scheduled and executed accordingly. We further designed a synthesis tool chain that automatically synthesizes the heterogeneous DPN to the open computing language (OpenCL) based implementation which is platform-independent and can be deployed on various commercial off-the-shelf (COTS) target platforms.

A dataflow process network (DPN) is a system of concurrent processes which communicate with each other through statically determined and buffered point-to-point connections. While the general model of computation (MoC) does not impose further restrictions, many different subclasses of DPNs have been considered over time like Kahn process networks, cyclo-static networks and synchronous dataflow networks. These classes differ in the kinds of behaviors of the processes that are precisely described based on how each process is triggered for an execution, and based on how each execution of a process consumes/produces data. A heterogeneous combination of particular kinds of processes can be effectively used to model different components of a system with different kinds of MoCs. Such a composition of dataflow processes within a network is termed as heterogeneous DPN. There are design tools for modeling like Ptolemy and FERAL that support different MoCs including particular classes of DPNs by the use of so-called directors. However, design tools for synthesis are usually restricted to the weakest classes of DPNs, i.e., cyclo-static and synchronous DPNs. In this paper, we present an extendable model-based design framework called SHeD for automatic -software synthesis of heterogeneous -DPNs. SHeD supports different kinds of DPN processes and therefore also different kinds of MoCs. To this end, SHeD proposes a general DPN model that is used with specific definitions and constraints to formulate the precise classes of DPNs. Also, it provides a tool chain, including different specialized code generators for specific MoCs, and a runtime system that finally maps models using a combination of different MoCs on the target hardware. We demonstrate the effective use of SHeD by a case study of a distributed automotive research platform.

The RVC-CAL language is used for implementing dataflow process networks (DPNs), i.e., distributed systems of actors. The behavior of an actor is defined by a set of actions which can consume input tokens and produce output tokens. RVC-CAL DPNs can offer parallelism both at the level of actors and at the level of actions. To efficiently execute these models on a target hardware, it is important to generate parallel code based on the entire parallelism provided by these two levels. In this paper, we discuss criteria for the generation of parallel software from RVC-CAL models based on the potential parallelism of modeled behaviors. The approach considers both the coarse-grained (task-parallel) execution of actors using multithreading and the fine-grained (data-parallel) execution of their actions using the open computing language (OpenCL) or even a higher-level layer of OpenCL, namely SYCL. The methodology is validated by benchmarks on OpenCL abstracted hardware platforms. Based on the experimental results, the methodology is evaluated for efficiency (performance) in comparison with a pure multithreaded C++ approach and a well-known reference framework.

In general, model-based design flows start from hardware-agnostic models and finally generate code based on the used model of computation (MoC). The generated code is then manually mapped with an additional non-trivial deployment step onto the chosen target architecture. This additional manual step can break all correctness-by-construction guarantees of the used model-based design, in particular, if the chosen architecture employs a different MoC than the one used in the model. To automatically bridge this gap, we envisage a holistic model-based design framework for heterogeneous synthesis that allows the modeling of a system using a combination of different MoCs. Second, it integrates the standard hardware abstractions using the Open Computing Language (OpenCL) to promote the use of vendor-neutral heterogeneous architectures. Altogether, we envision an automatic synthesis that maps models using a combination of different MoCs on heterogeneous hardware architectures. This paper evaluates the feasibility of incorporating OpenCL as a standard hardware abstraction for such a framework. The evaluation is presented as a case study to map a synchronous application on different target architectures using the OpenCL specification.

Model-based design flows for embedded systems have been introduced to allow late design changes while still keeping tight time-to-market deadlines. In general, these design flows start with abstract models and refine these to a final implementation maintaining already implemented properties. However, essentially all of these design flows suffer from a deployment gap in the sense that the finally generated files are general program files which assume a particular model of computation (MoC) that may not be provided by the chosen target architecture. For this reason, the final deployment is usually a non-trivial manual design step that can break all correctness-by-construction guarantees of the previous model-based design. In this paper, we therefore introduce the idea of MoC drivers which wraps the real sensor and actuator interaction in a shell that provides the MoC of the generated software. As a particular example, we discuss in this paper how MoC drivers bridge the deployment gap between automatically generated dataflow programs and event-driven behaviors of the target architecture. The approach is illustrated with a Speedometer application on a distributed automotive embedded platform.

In this paper, we show how code can be generated at different levels of abstraction from a single source description. To this end, we use a model-driven development tool called Averest that is based on a synchronous programming language. We illustrate our approach by means of a case study from the domain of distributed real-time automotive embedded systems. This paper focuses thereby mainly on the use of the Averest toolkit to generate code at different levels of abstraction.