A single-board 14.3-MOPS (million operations per second) video signal processor module (VSPM) has been developed. The module is fully microprogrammable and processes up to a 128 pel*128 pel subimage every 16.7 ms. Using a number of homogeneous VSPMs aligned in parallel, a real-time video signal processing environment is provided on the basis of an overlap-save or overlap-add technique. An experimental system has been constructed in order to demonstrate the signal processor approach's effectiveness for video signals by implementing picture coding algorithms. Due to software control capability, various kinds of picture coding techniques can be evaluated by the system.>

Two important functional LSIs for the realtime Video Signal Processor (VSP) have been developed. One is the Pipelined Arithmetic Unit (PAU) and the other is the Address Generation Unit (AGU). The PAU chip employs a flexible pipelined architecture optimized for L1 or L2-norm distance calculation, used in a wide variety of image processing. The AGU chip, including 15-word register file for pointer alteration, offers a user-friendly two dimensional pointer addressing. A realtime Video Signal Processor Module (VSPM), composed of one PAU, four AGUs and memories, has been implemented for multiprocessor VSP configuration. Thanks to software control capability, various kinds of picture coding techniques can be evaluated by the system.

A real-time video signal processor (VSP), suitable for VLSI implementation, is proposed. In order to obtain software controllability for video signal processing in a real-time environment, the VSP employs a multiprocessor configuration, where a plural number of video signal processing modules (VSPMs) are connected to input, output and feedback buses. Each VSPM processes its own assigned sub-images without communicating from/to other VSPMs. As the VSP needs no overhead for VSPM communication, the number of VSPMs involved does not affect the VSP system performance. The homogeneous processor based approach, employed in VSP, will become the most suitable LSI implementation methodology in the near future, due to processor module regularity and system flexibility.