This research examines the problem of scheduling robotized cluster tools under the operational requirement of controllingwafer flow time. Recently, in wafer fabs, the wafer flow time is recognized as an important factor that impacts the quality level of semiconductor end-products. We first establish a theoretical basis for the analysis of the wafer flow time in cluster tools, and then we prove that the wafer flow time can be significantly reduced by regulating the wafer loading level inside the tool. It is also shown that there is a tradeoff between the wafer flow time and tool productivity, and thus the reduction of the wafer flow time can lead to an increased tool cycle time. To manage this tradeoff effectively, we present a scheduling rule by which the wafer flow time can be effectively controlled while minimizing the productivity loss caused by the increased tool cycle time. The introduced scheduling approach provides practical insights and numerical validation, offering semiconductor manufacturers a viable strategy to enhance both wafer quality and production efficiency.

A cluster tool, widely used for semiconductor wafer fabrication, consists of several single-wafer processing chambers and a wafer handling robot. A chamber for critical processes is periodically cleaned for removing chemical impurities to reduce quality risk due to extreme circuit width shrinkage. We examine the problem of determining a cleaning plan for dual-armed cluster tools with general chamber cleaning periods$k_{i} > 1$for chamber$i$using the popular swap sequence to minimize the cycle time. We derive conditions for which the popular swap sequence minimizes the tool cycle time regardless of the cleaning plan. For the other cases, we develop a cleaning rule named DGC(Dispersing and Gathering Cleaning) that disperses cleaning operations along the robot cycle and gathers the cleaning operations that are interlaced along the robot cycle. For parallel flows with a single process step, we develop a closed-formula for the cycle time and prove that DGC minimizes the cycle time for the swap sequence. We also present conditions under which the swap sequence with the cleaning rule achieves the minimum cycle time compared to all other sequences and cleaning plans. For serial wafer flows, we show that DGC minimizes the cycle time when the cleaning period and the cleaning time are the same for all process steps. We also show by experiments that the proposed DGC effectively reduces the cycle time for the other general cases.Note to Practitioners—Our proposed cleaning rule can significantly improve the tool cycle time and regulate wafer flow times. It is easily applied or adapted to and effective for most wafer flow patterns, sequences, and tool architectures.

This study proposes a modeling and scheduling methodology to solve the optimization problem of base (an annealing facility) reflecting various field requirements. Our main intention is to achieve a virtual loading simulation and instruction automation. In order to increase the productivity in an annealing line, the process should be executed by loading as many coils as possible into the base. Nonetheless, when loading into the base, several characteristics of both coils and base, such as subdivided an annealing cycle as well as process time, and so on, must be taken into consideration. As a result, we expect to build big data by collecting on-site facility data of the annealing line based on real-time IoT technology and industry standard protocols.

In this research, we examinefeedback control-based cluster tool scheduling methods to maintainconsistentwafer sojourn times when a tool is subject torandom disruptive events. In our previous work, we proposed a feedback control design that regulates wafer sojourn times not to exceed the upper limits on wafer delays in a deterministic processing environment. Although such a feedback controller may ensure that wafer delay upper limits are always satisfied, it does not necessarily guarantee that the tool always restores its initial tool state after the occurrence of time disruptive events. This article thus further examines under which conditions a feedback controller enforces the wafer sojourn times to bestabilizedin astochasticprocessing environment with unexpected random time disruptions.Note to Practitioners—In semiconductor manufacturing, excessive wafer sojourn times at wafer fabrication tools increase the risk of wafer quality failures. In particular, the wafer quality fluctuates when the sojourn times are inconsistent over different wafers. Therefore, in cluster tools, wafer sojourn times are often strictly regulated to be minimized or to remain constant with an objective of reducing the risk of wafer quality degradation. In this research, we examine a cluster tool scheduling framework that enables to maintain stable tool operations even when a tool is randomly disrupted by unexpected exceptional events.

Timed Petri nets (TPNs) have been widely used for modeling discrete-event systems of diverse manufacturing and service industries. In this article, we introduce a reachability tree-based optimization algorithm to optimize cyclic schedules of TPNs. In particular, we focus on a special class of cyclic schedules that are referred to as one-cyclic schedules, i.e., the algorithm efficiently finds the optimal one-cyclic transition firing schedule of a TPN. The proposed scheduling method can be robustly applied and extended to a number of different scheduling models since the methodology is not bounded to a specific domain. To enhance the computational performance, we establish a set of transition ordering constraints that can reduce the tree size during the search procedure. We evaluate the computational efficiency of the suggested algorithm by examining robotized manufacturing systems where one-cyclic schedules are popularly being used. It is numerically shown that the proposed algorithm is computationally more efficient than the previously studied Petri net-based optimization methods.Note to Practitioners—Resource scheduling is one of the most important managerial issues in diverse industrial systems. An optimal scheduling method for a certain industrial system is often locally developed by utilizing domain-specific operational properties. Although such domain-dependent knowledge can contribute to enhancing the computational efficiency of an optimization method, such an approach has a weak point that the method might not be applicable to scheduling problems of different industrial fields. Our motivation is to develop an algorithm for optimizing steady-state schedules that can be robustly applied for various types of discrete-event systems. The algorithm is developed on the basis of the Petri net modeling framework as it is widely being used for describing cyclic behaviors of diverse manufacturing systems, service systems, and social systems. It is experimentally shown that the proposed algorithm is computationally efficient compared with the existing cyclic scheduling methods.

We examine a scheduling problem for a dual-armed cluster tool that processes multiple similar wafer types concurrently. It has been recently proved that the well-known swap sequence, which is widely used for single wafer type processing, also minimizes the cycle time for concurrent processing. In this article, we wish to minimize wafer delays in a process chamber, which are critical to wafer quality degradation, while maintaining the minimum cycle time. In particular, we show that concurrent processing of wafers with different processing times complicates the analysis of wafer delays significantly, and the wafer delays can be remarkably reduced by finding a proper cycle plan which is the release sequence of different wafer types. We first characterize wafer delays for a given cycle plan by analyzing the circuits of the timed event graph (TEG) model. From this, we prove that concurrent processing of wafers may cause a significant workload imbalance between parallel chambers of a process step, and hence the wafer delays increase substantially. We present that the wafer delays are minimized by a cycle plan that evenly balances workloads between parallel chambers. We also propose how wafer loading task at each process step has to be postponed to meet wafer delay constraints while maintaining the minimum cycle time.Note to Practitioners—Wafer quality control has become an essential fab operational problem in semiconductor manufacturing industry. In cluster tools, which are dominantly being used for diverse wafer fabrication stages, it has been proven that the wafer delays within process chambers have a crucial impact on the wafer quality. Accordingly, modern fabs have introduced stringent quality control to regulate wafer delays in cluster tools. In this research, we propose a scheduling strategy to minimize the wafer delays when a cluster tool concurrently processes multiple wafer types. We first show that the release sequence of different wafer types significantly impacts the wafer delays under concurrent processing, and we then propose how these wafer delays can be minimized by finding the optimal wafer release sequence.

A cluster tool consists of several single-wafer processing chambers and a wafer handling robot. A wafer has to wait within a chamber after being processed there until it is unloaded by the robot. Such wafer delays may cause wafer quality degradation or variability due to residual gases and heat in the chamber. The tool operation schedule has to maintain identical timing patterns or schedules for each cycle so as to keep wafer delays constant for every wafer. However, at the beginning of the tool operation, the tool is in an empty state and hence we need to make the tool reach such steady schedule by loading wafers into the tool. In this article, we develop a method of scheduling the robot tasks during the start-up period of a cluster tool to reach a target steady schedule quickly as possible. To do this, we model the behaviors of a cluster tool using timed Petri nets and linear system matrices in the max-plus algebra. By analyzing the matrices, we first identify a class of steady schedules which can be reached from the empty tool. We develop the matrices that explain the schedule evolution of the start-up period before reaching the steady period. By examining the matrices, we develop a method of choosing the most desirable one from such class of reachable steady schedules that can be achieved in the minimum time. We also prove that the schedule also minimizes the time duration of the close-down. Finally, we present computational experiments.

A cluster tool consists of several single-wafer processing chambers and a wafer-handling robot. Cluster tools are widely used for wafer fabrication in semiconductor manufacturing fabs. As the circuit width shrinks down to below 20 or even several nanometers, wafer waiting within a chamber after processing becomes more critical to wafer quality due to residual gases and heat. Conventional tool scheduling rules, such as the swap sequence and the backward sequence, may not satisfy strict upper limits on wafer delays, especially when process times fluctuate randomly. We examine a scheduling problem for cluster tools with strict upper limits on wafer delays under process time variation. We propose a new class of schedules, which not only keeps timing patterns steady as possible but also adapts timing of tasks in response to process time variation so as to satisfy wafer delay constraints robustly. We also derive conditions for which there exists such a schedule. We develop a mixed-integer programming model to find an optimal schedule among such adaptive schedules. By numerical experiments, we show that the proposed scheduling method can effectively cope with tight wafer delay constraints even under large process time variations.

As the order size for modern fabs tends to be smaller, fabs wish to process a class of similar wafer lots at a tool concurrently to reduce the work-in-progress lots as well as the total manufacturing lead time. We examine a scheduling problem for a dual-armed cluster tool that simultaneously produces multiple wafer types with identical wafer flow patterns but different process times. We prove that the conventional swap sequence, which is optimal and prevalently being used for single-wafer-type processing, is also optimal for such concurrent processing. We then propose a way of determining a release sequence of wafer types into the tool, called cycle plan, that maximizes the utilization of parallel chambers and hence increases the tool throughput rate. We present conditions for which the parallel chambers are shared by all wafer types and their workloads are evenly balanced so as to maximize the throughput rate. We also report the experimental results.

Robotized cluster tools for semiconductor wafer fabrication may have a wafer wait within a processing chamber after processing there until the wafer is unloaded from the chamber by a robot. Such wafer delays cause wafer quality degradation or variability due to residual gases and heats within the chamber. There have been numerous works on characterizing wafer delays and scheduling under upper limits on wafer delays while presuming that the tools are operated by well-known simple robot task sequences such as swap or backward sequences. However, when the wafer delay constraints are tight, there may not be feasible schedules for such sequences. We wish to know whether there can be alternative robot task sequences which can satisfy such tight wafer delay constraints. In this paper, we identify a new class of robot task sequences that can better satisfy tight wafer delay constraints than the conventional swap or backward sequences while keeping the same minimum tool cycle time. By examining the circuits of timed event graph (TEG) models for the tool operation behaviors in many different robot task sequences, we identify that such robot task sequences do not make interferences between the work cycles of the resources such as the robot and chambers. The resource interference can cause delays in the work cycles, and hence increase the wafer delays or the tool cycle time. To prove this, we examine circuits in an extended TEG model, a negative event graph, which incorporates time constraints as negative places and tokens. From this, we derive closed-form conditions for which such sequences are feasible against given wafer delay constraints. By experiments, we show that the proposed new sequences have shorter wafer delays, and hence better satisfy tight wafer delay constraints than conventional sequences. Note to Practitioners-As circuit widths shrink down to several nanometers, cluster tools for semiconductor fabrication require extreme process quality control. Even wafer delays within processing chambers of cluster tools can cause wafer quality degradation and variability. Therefore, it is desirable for cluster tools to have much shorter wafer delays. However, conventional sequences such as the swap and backward sequences, which are being prevalently used in practice, may not satisfy tight wafer delay constraints. Our proposed sequences, which are as simple as the conventional sequences, have much shorter wafer delays while keeping the same minimum tool cycle time.

Circuit widths and nodes of semiconductor wafers have been continually shrinking down to less than 20 nm. Therefore, modern wafer fabs enforce extremely strict process control to prevent wafer quality failures. A wafer processing chamber is now frequently cleaned to remove residual chemicals and impurities. Yu et al. show that such cleaning operations significantly change the tool operation of single-armed cluster tools, and they suggest an idea of partial wafer loading to improve the tool throughput under cleaning requirements. However, little is known about how a dual-armed tool could be effectively scheduled when chamber cleaning exists. A dual-armed robot allows more flexible tool operational sequences, and hence, the scheduling problem becomes further complicated and challenging. In this paper, we propose a scheduling method by which the dual arms can be properly exploited for better tool productivity. We show that the suggested hybrid sequence significantly reduces the tool cycle time as compared to previously developed scheduling methods. Through this research, we conclude that the productivity gain of the dual arms against single arm is more significant when chambers are cleaned.

As wafer circuit widths shrink down, wafer fabrication processes require stringent quality control. Therefore, fabs recently tend to clean a chamber after processing each wafer, in order to remove chemical residuals within the chamber. Such chamber cleaning, called purge operation, increases scheduling complexity in robotized cluster tools. In this paper, we examine scheduling problems of single-armed cluster tools with purge operations for series-parallel chambers. By extending the wellknown backward sequence, we propose a backward(z) sequence that allows partial loading for parallel chambers, where vector z specifies how many chambers zi of each process step i are kept empty for cleaning. We then propose a way of finding optimal vector z* and identify when backward(z*) achieves the minimum cycle time among all possible sequences. We present experimental results on the accuracy of backward(z*).