The design and performance characteristics of a 128×64 MOS transistor memory is given. The storage cell used operates with a low standby power, 0.1 mW. The memory operates with a 12-ns access time, 35-ns read cycle time, and a 60-ns write cycle time.

Because of a multiplicity of conflicting requirements, sense amplifier design is probably the most difficult circuit problem in a large, high-speed digital computer memory. The requirements include absence of pattern sensitivity, controllable input impedance, a wide band pass, stable gain, high common mode rejection, the ability to handle bipolar signals, stable reference levels, a fast comparator, low threshold level, and, one hopes, low cost. This paper discusses a new circuit which fulfills these requirements with simplicity. Intended for large size (> 1000 words) random access core and thin-film memories, it is capable of handling, for example, a 50-mv ``1'' with approximately 50-nsec delay for transmission and comparison. Common mode signals of as high as 10 volts do not affect discriminator performance. Two key features of the circuit are the use of a dc-coupled, ``long-tail pair'' preamplifier and a pair of tunnel diodes as the discrimination elements. The dc-coupled differential preamplifier provides high common mode rejection, stable gain, is pattern insensitive, and has the ability to handle bipolar signals. The tunnel diode provides a superior discriminator, since it is fast, and has a low-level threshold which is controllable and stable with temperature variations. Thus, requirements on the magnitude and stability of the preamplifier gain are less severe. Design equations are derived and a complete dc worst-case analysis is performed. Variations in the circuit for several specific applications and experimentally determined performance data are described. The generalized problem of a tunnel-diode discriminator used with a preamplifier is treated in Appendix II.