Caches are widely used in FPGA accelerators such as SmartNICs to hide DRAM latency, but conventional designs treat caches as passive storage. When workloads require read–modify–write (RMW) updates – such as flow tables, counters, or per-connection state – existing cache IPs force designers to either stall the pipeline or duplicate hazard-handling logic outside the cache. Both approaches waste bandwidth, complicate datapath design, and require extensive verification.We propose EZCache, a new FPGA cache IP that integrates programmable action blocks directly into the cache pipeline. These blocks perform user-defined operations on cached data in place, allowing RMW updates to complete without stalling other operations or exposing hazards to surrounding logic. By embedding compute into the cache, EZCache transforms it from a passive buffer into an active architectural primitive suitable for a wide range of FPGA accelerators.EZCache is fully parametric in associativity, latency, throughput, and action complexity, enabling a single design to support diverse workloads and memory systems. This parametric abstraction allows the surrounding datapath to remain stable even as cache configurations, action semantics, and external memories evolve across hardware generations. EZCache has been deployed across five generations of SmartNICs and millions of devices worldwide, proving both its maturity and its impact in production. Results across multiple FPGA platforms show EZCache’s generality and efficiency, establishing it as a new foundation for cache-based acceleration in reconfigurable systems.

Distributed training of artificial intelligence models, such as Large Language Models (LLMs), generates highly structured and intense traffic patterns between GPUs, with synchronous and repetitive flows that can easily cause congestion and bottlenecks in data center networks. In this context, currently adopted protocols, such as RoCEv2, show significant limitations in the presence of bursty traffic and low entropy, compromising overall system efficiency. Segment Routing over IPv6 (SRv6) offers a programmable mechanism to steer AI workload traffic along explicitly chosen paths, enabling precise and congestion-aware routing under dynamic conditions. Lightweight monitoring modules can detect congestion conditions in real time and report them to the orchestrator or NICs, enabling dynamic rerouting decisions without requiring control-plane signaling or state in the fabric. SRv6 micro-segment (uSID) encoding allows the NIC to steer traffic along alternate, congestion-free paths simply by updating the IPv6 destination address, preserving RoCEv2 semantics while ensuring rapid adaptability. This work provides a practical implementation and experimental validation of the recent IETF Internet-Draft “SRv6 for Deterministic Path Placement in AI Backends”, demonstrating its feasibility and performance benefits in RoCEv2-based infrastructures. The results highlight the potential of SRv6 as a practical and vendor-agnostic solution to enhance networking efficiency in modern AI datacenters.

The network programming model of the Segment Routing (SRv6) architecture offers the possibility to define new functions aiming at improving the network performance. In this paper we introduce SRv6 Live-Live, a new behavior for the SRv6 data plane. SRv6 Live-Live is based on two primitives: i) traffic duplication, performed at the ingress node, and ii) the traffic de-duplication, executed at the egress node. The proposed behavior is suitable for the service provisioning of traffic flows having stringent requirements in terms of reliability, low delay and high throughput. Our preliminary performance evaluation, conducted in an emulated environment and realized by using a prototype implementation based on P4, shows that SRv6 Live-Live enhances the performance of the selected traffic flows in challenging network scenarios, characterized by high level of packet corruption/loss and large values of bandwidth-delay products.

Software-Defined Wide Area Networks (SD-WANs) are used to provide services to enterprises with geographically dispersed locations in a flexible and efficient way. We focus on SD-WAN services based on the Segment Routing over IPv6 (SRv6) technology. Performance Monitoring solutions are needed in SD-WANs to detect performance degradation and outages, and optimize network operations. In this paper, we describe a high performance solution for end-to-end delay monitoring for SRv6 based SD-WAN services. The proposed solution leverages the Simple Two-way Active Measurement Protocol (STAMP) to monitor the delay of an SRv6 path between two nodes called STAMP Session-Sender and Session-Reflector. We describe three implementations of the STAMP Session-Sender and Session-Reflector for a Linux software router and compare their performance. In particular, two implementations are based on user space processing and one is based on eBPF. The results show that the eBPF-based implementation outperforms the user space implementations and has a negligible impact on the forwarding capacity of the Linux software router.

The Segment Routing (SR) architecture is based on source routing. Within an SR enabled network, a list of instructions called segments can be added to the packet headers to influence the forwarding and the processing of the packets. In SRv6 (Segment Routing over IPv6 data plane) the segments are represented with IPv6 addresses, which are 16 bytes long. There are some SRv6 service scenarios that may require to carry a large number of segments in the IPv6 packet headers. Reducing the size of these overheads is useful to minimize the impact on MTU (Maximum Transfer Unit) and to enable SRv6 on legacy hardware devices with limited processing capabilities that could suffer from the long headers. In this paper we present the Micro SID solution for the efficient representation of segment identifiers. The proposed Micro SID solution has been implemented on three different architectures (VPP, Linux, P4) and interoperability tests have been performed. We also analyze the reduction of the header size that can be achieved with Micro SIDs and compare it with other proposals for segment list compression. Our results show that the header size can be reduced up to 75%. Finally, we mention that a fundamental asset of the proposed Micro SID solution is the full compatibility and seamless interoperability with existing SRv6 architecture.

Network services are essential in modern networks. They are a crucial part of today's network operation and ensure customizable, reliable, and secure communication. This being said, they also have a noteworthy drawback: they are consumed in a static manner. As a consequence, the management of network services is too complex and thus expensive and error-prone. Furthermore, this static processing cannot react to network changes: a service outage, a link failure, or any other network events can result in connectivity loss for customers and has to be usually resolved manually. This paper proposes a practical solution for dynamic, event-triggered, and fast path calculations that program services and permit a so-called service chain. To allow programming services directly in the backbone of a service provider network is solving the static service consumption in service provider networks. The solution is based on the functionalities of Segment Routing over IPv6 (SRv6 in short), which implements the source-based routing paradigm with the native IPv6 encapsulation. Our focus was set on finding the best reliable and fast way to calculate the best path through the given service instances. Because service provider networks are constantly growing, an algorithm has to be found and implemented so that the growth of the network has no impact on the calculation performance. A complete cloud-native development approach has been taken to create the application as elastic and fault-tolerant as possible. Thanks to the cloud-native approach, the application can be portable in a different environment, in an on-premise datacenter, or directly in the public cloud.

Segment Routing (SR) is a form of loose source routing. It provides the ability to include a list of instructions, called segments, in the packet header. The SR architecture has been first implemented with the MPLS (SR-MPLS) data plane and then, quite recently, with the IPv6 data plane (SRv6). SRv6 is a promising solution to support advanced services such as Traffic Engineering, Service Function Chaining and Virtual Private Networks. The SRv6 data plane is supported in many different software forwarding engines including the Linux kernel and the Vector Packet Processor (VPP), as well as in hardware devices. In this paper, we present SRPerf, a performance evaluation framework for software and hardware implementations of SRv6. SRPerf is able to perform different benchmarking tests such as throughput and latency. The architecture of SRPerf can be easily extended to support new benchmarking methodologies as well as different SRv6 implementations. We have used SRPerf to evaluate the performance of two SRv6 implementations: Linux kernel and VPP. SRPerf is a valuable tool in the context of modern forwarding engines where new features can be added at fast pace, as it helps experimenters to validate their work. In this work, we have leveraged SRPerf to validate the implementation of some SRv6 behaviors in the Linux kernel and we have discovered and fixed some implementation flaws, making available the fixed code.

Segment Routing over IPv6 (SRv6 in short) is a networking architecture suitable for both IP backbones and datacenters. The research, standardization and implementation of this architecture are actively progressing and SRv6 is already adopted in a number of large scale deployments. Effective solutions for Performance Monitoring (PM) of SRv6 networks are strongly needed and there is a lot of activity in this area. A full blown Performance Monitoring solution needs to include: i) Data Plane (as needed to measure metrics such as packet loss and delay); ii) Control Plane (to send commands to the monitoring entities in the nodes); iii) Management Plane (e.g., to collect the measured metrics). Moreover, Big-Data tools and solutions can be applied inside or above the traditional Management Plane boundaries to store and analyze the collected data. In this article we describe SRv6-PM, a solution for Performance Monitoring of SRv6 networks that deals with all the aspects discussed above. SRv6-PM features a cloud-native architecture that supports: i) the ingestion, processing, storage and visualization of PM data using Big-Data tools; ii) the SDN-based control of network routers to drive the performance monitoring operations. In particular, we focus on Loss Monitoring and consider a solution capable of tracking single packet loss events operating in near-real time (e.g., with a time granularity in the order of 10-20 seconds). SRv6-PM is released as open source. We offer a re-usable and extensible platform that can be automatically deployed in different environments, from a single host to multiple servers on private/public clouds and includes a set of Big-Data tools and the SDN control plane. We also provide a reproducible Data Plane environment for PM experiments in SRv6 networks based on the Mininet emulator.

The Segment Routing (SR) architecture is based on loose source routing. A list of instructions, called segments can be added to the packet headers, to influence the forwarding and the processing of the packets in an SR enabled network. In SRv6 (Segment Routing over IPv6 data plane) the segments are represented with IPv6 addresses, which are 16 bytes long. There are some SRv6 service scenarios that may require to carry a large number of segments in the IPv6 packet headers. Reducing the size of these overheads is useful to minimize the impact on MTU (Maximum Transfer Unit) and to enable SRv6 on legacy hardware devices with limited processing capabilities that could suffer the long headers. In this paper we present the Micro SID solution for the efficient representation of segment identifiers. With this solution, the length of the segment list can be drastically reduced.

We consider the IPv6 Segment Routing (SRv6) technology for Service Function Chaining of Virtual Network Functions (VNFs). Most of the VNFs are legacy VNFs (not aware of the SRv6 technology) and expect to process traditional IP packets. An SR proxy is needed to support them. We have extended the implementation of SRv6 in the Linux kernel, realizing an open source SR-proxy, referred to as SRNK (SR-Proxy Native Kernel). The performance of the proposed solution (SRNKvl) has been evaluated, identifying a poor scalability with respect to the number of VNFs to be supported in a node. Therefore we provided a second design (SRNKv2), enhancing the Linux Policy Routing framework. The performance of SRNKv2 is independent from the number of supported VNFs in a node. We compared the performance of SRNKv2 with a reference scenario not performing the encapsulation and decapsulation operation and demonstrated that the overhead of SRNKv2 is very small, on the order of 3.5%.

This paper presents an architecture to support Vir- tual Network Functions (VNFs) chaining using the IPv6 Segment Routing (SR) network programming model. Two classes of VNFs are considered: SR-aware and SR-unaware. The operations to support both SR-aware and SR-unaware VNFs are described at an architectural level and we propose a solution for SR-unaware VNFs hosted in a NFV node. An Open Source implementation of the proposed solution for a Linux based NFV host is available and a set of performance measurements have been carried out in a testbed.

The paper investigates the performance of an HMM-based text-independent speaker recognition system under different model and feature combinations for matched and mismatched speech coding conditions. The effects of changing the HMM topology and acoustic features is first investigated. Training and testing the models using only the voiced segments of the samples is then considered. The best model structure in each topology is then used to test the effects of speech codecs like G729 at 8 kb/s and G723.1 at 5.3 and 6.3 kb/s, used in multimedia applications, on the performance of both matched and mismatched conditions. To improve the performance in mismatched conditions, a MAP-based adaptation with different amounts of coded training data and a diagonal affine transform for adapting the coded cepstral features to the original PCM cepstral features are investigated. Results show that the proposed techniques improve speaker recognition performance and produce comparable results to the matched condition test.