The globalization of the integrated circuit (IC) supply chain has increased the risk of IC piracy. Analog and mixed-signal (AMS) ICs are particularly vulnerable, as their design demands specialized expertise and multiple tapeouts to meet specifications, while they have limited automation support and inflexible portability across technology nodes, making them valuable intellectual assets and attractive targets for piracy. IC locking has emerged as an effective countermeasure, with several AMS IC locking paradigms proposed to date. The core idea is to embed a key mechanism within the AMS IC to control its functionality, treating the key as the designer's secret. Correct operation is achieved only when the valid key is applied, while any incorrect key renders the circuit non-functional. Existing locking solutions for purely analog blocks face the challenge of ensuring this dual objective. In this work, we propose an optimizationbased methodology that jointly synthesizes the target circuit and its key mechanism, ensuring the objective is deterministically achieved. The methodology is validated on two widely used AMS circuits: a bandgap reference and an operational amplifier.

The growing demand for high-performance analog circuits requires innovative design methodologies that accelerate the design process while maintaining accuracy and reliability. Machine Learning (ML) techniques have recently emerged in Inte grated Circuit (IC) design, leveraging their powerful modeling capabilities across different design stages. This paper introduces a simulation-free design automation methodology using Artificial Neural Networks (ANNs) to enhance Flash-ADC design work flows. The proposed approach adopts a top-bottom hierarchical design strategy: ANNs replace simulators and designers, elim inating the need for time-consuming simulations or excessive design iterations. To demonstrate the method, an 8-bit Flash-ADC was synthesized. The results show that the proposed framework significantly reduces computational overhead and accelerates the design process, achieving ultra-fast within less than one second. The study presents a generalized approach for ADC design and a hybrid testbench setup for analog optimization, offering a scalable solution for other complex systems.

Thanks to the enhanced computational capacity of modern computers, even sophisticated analog/radio frequency (RF) circuit sizing problems can be solved via electronic design automation (EDA) tools. Recently, several analog/RF circuit optimization algorithms have been successfully applied to automatize the analog/RF circuit design process. Conventionally, metaheuristic algorithms are widely used in optimization process. Among various nature-inspired algorithms, evolutionary algorithms (EAs) have been more preferred due to their superiorities (robustness, efficiency, accuracy etc.) over the other algorithms. Furthermore, EAs have been diversified and several distinguished analog/RF circuit optimization approaches for single-, multi-, and many-objective problems have been reported in the literature. However, there are conflicting claims on the performance of these algorithms and no objective performance comparison has been revealed yet. In the previous work, only a few case study circuits have been under test to demonstrate the superiority of the utilized algorithm, so a limited comparison has been made for only these specific circuits. The underlying reason is that the literature lacks a generic benchmark for analog/RF circuit sizing problem. To address these issues, we propose a comprehensive comparison of the most popular two evolutionary computation algorithms, namely Non-Sorting Genetic Algorithm-II and Multi-Objective Evolutionary Algorithm based Decomposition, in this article. For that purpose, we introduce two ad hoc testbenches for analog and RF circuits including the common building blocks. The comparison has been made at both multi- and many-objective domains and the performances of algorithms have been quantitatively revealed through the well-known Pareto-optimal front quality metrics.

Despite the parallelism and sparsity in neural network models, their transfer into hardware unavoidably makes them susceptible to hardware-level faults. Hardware-level faults can occur either during manufacturing, such as physical defects and process-induced variations, or in the field due to environmental factors and aging. The performance under fault scenarios needs to be assessed so as to develop cost-effective fault-tolerance schemes. In this work, we assess the resilience characteristics of a hardware accelerator for Spiking Neural Networks (SNNs) designed in VHDL and implemented on an FPGA. The fault injection experiments pinpoint the parts of the design that need to be protected against faults, as well as the parts that are inherently fault-tolerant.

The error-resiliency of Artificial Intelligence (AI) hardware accelerators is a major concern, especially when they are deployed in mission-critical and safety-critical applications. In this paper, we propose a neuron fault tolerance strategy for Spiking Neural Networks (SNNs). It is optimized for low area and power overhead by leveraging observations made from a large-scale fault injection experiment that pinpoints the critical fault types and locations. We describe the fault modeling approach, the fault injection framework, the results of the fault injection experiment, the fault-tolerance strategy, and the fault-tolerant SNN architecture. The idea is demonstrated on two SNNs that we designed for two SNN-oriented datasets, namely the N-MNIST and IBM's DVS128 gesture datasets.

The deployment of Artificial Intelligence (AI) hardware accelerators in a variety of applications, including safety-critical ones, requires assessing their inherent reliability to hardware-level faults and developing cost-effective fault tolerance techniques. This entails performing large-scale fault simulation experiments. However, transistor-level fault simulation is prohibitive and fault simulation should be carried out at a higher abstraction level. In this work, we focus on spiking neural networks (SNNs), and we follow a bottom-up approach starting from transistor-level simulations for developing a neuron behavioral-level fault model that can be readily employed for performing behavioral-level fault simulation of deep SNNs.

Performance of analog circuits degrades over time due to several time-dependent degradation mechanisms. Due to the increased aging problems in ever-shrinking dimensions, reliability of complementary metal-oxide-semiconductor analog circuits has become a major concern. Overdesign is a popular aging-aware circuit design approach, where circuit operation is guardbanded by choosing the design point beyond the optimal region. For the sake of reliability, power consumption and chip area are sacrificed in this approach, which is undesirable considering strict energy limitations in modern applications. Conversely, Sense and React (S8R) approach serves the same purpose without any additional power consumption, in which degradation of circuit features is detected by online monitoring and recovered immediately. Furthermore, such systems enable remote control and healing of circuits. However, design of an S8R system is quite complicated. In particular, determination of efficient aging signatures and design of recovery strategy are highly challenging problems. This study thoroughly discusses the design process of S8R systems and proposes computer-aided-design-based design strategies that reduce the designer effort considerably. A novel design automation tool for S8R systems was developed, in which signature selection and recovery determination were integrated. To demonstrate proposed design strategies, two different S8R systems are implemented, simulated, and discussed in detail.

With the growing use of analog circuits in sensor systems for internet of things applications, estimation of their yield has become critical in order to increase the efficiency of large volume manufacturing. In this paper, a methodology to estimate the yield of analog circuits beyond 95% is proposed. The methodology is based on an algorithm that uses adaptive sampling to approach the “tail” region of the initial distribution which contains the dysfunctional units. These units do not satisfy the initial design targets thereby lowering the yield. An inverter and a two-stage operational amplifier have been used to verify the methodology where the reference distribution is based on 10^6 samples for both circuits. Simulation results reveal that the accuracy for 95%, 98%, and 99% yield has been compromised by less than 2.1%, 5.7%, and 7.4%, respectively, whereas the computation cost is reduced by 20x.

This study presents a parasitic-aware RF circuit synthesis tool, in which layout-induced parasitics of passive devices are captured by using sophisticated equivalent models for them. Recently, analog circuit design has been fully automated, where a circuit sizing is followed by a layout generator. However, there is often a discrepancy between synthesis and post-layout results, especially for RF applications, due to severe layout-induced parasitics of passive devices. Therefore, a number of iterations between circuit sizing and layout generator are required to achieve a fully satisfactory solution, which lead to dramatically increased synthesis times. The proposed approach provides more realistic results at the sizing part via optimizing physical parameters of passive devices, rather than their electrical values, thus, iteration count between circuit sizing and layout generation can be kept at a minimum.

This paper proposes a novel multi-objective yield aware analog sizing tool that utilizes scrambled Quasi Monte Carlo (QMC) approach for efficient yield estimation and Strength Pareto Evolutionary Algorithm-2 (SPEA2) as a search engine. Analog circuit sizing tools have been utilized for the last two decades to overcome challenging trade-offs in analog circuit design. However, due to the variation phenomenon, some solutions at the Pareto front (PF) move towards the suboptimal region. To overcome this issue, yield aware optimization tools, where yield is given as a new design objective, have been proposed in the last decade. Conventionally, Monte Carlo (MC) approach has been used for the yield estimation. However, large sized MC analysis is a highly inefficient and time consuming process because of the numerous simulations performed during the optimization process. Rather than conventional MC, using QMC, which utilizes Low Discrepancy Sequences (LDS), enhances the synthesis time since, it promises low estimation errors with fewer number of simulations. Thanks to the QMC based variability analysis and multi-objective search engine, a yield aware PF that allows the designer to access all robust solutions can be obtained within an acceptable synthesis time.

The design of complex analog circuits by using flat optimization-based approaches is inefficient, even impossible, due to the high number of design variables and the growth of the cost of performance evaluation with the circuit size. Over the past two decades, top-down hierarchical design approaches have been developed and applied. They are based on hierarchical circuit decomposition and specification transmission from top-level to lower level blocks. However, such specification transmission is usually performed with little knowledge on the feasibility of the specifications, leading, therefore, to costly redesign iterations. Even if the specification transmission is successful, there is no guarantee that it is optimal in terms of e.g., power consumption or area occupation. To palliate this problem, two novel model-based hierarchical synthesis methods are proposed in this paper: ModelBased Hierarchical Optimization (MBHO) and Improved ModelBased Hierarchical Optimization (IMBHO). They are based on the concurrent design at higher and lower hierarchical levels and appropriate communication between the different processes. Experimental results on a filter example comparing the new approaches and the conventional top-down design approach are provided.

Failure due to aging mechanisms is an important concern for RF circuits. In-field aging results in continuous degradation of circuit performances before they cause catastrophic failures. In this regard, the lifetime of RF/analog circuits, which is defined as the point where at least one specification fails, is not just determined by aging at the device level, but also by the slack in the specifications, process variations, and the stress conditions on each of the devices. In this paper, we present a methodology for analyzing, monitoring, and mitigating performance degradation in cross-coupled LC oscillators caused by aging mechanisms in MOSFET devices. At design time, we identify reliability hot spots and concentrate our efforts on improving these components. We aim at altering degradation patterns of important performance parameters, thereby improving the lifetime of the circuit with low area and no performance impact. We use simulations based on verified aging models to evaluate the monitoring and mitigation techniques and show that the proposed methods can increase the lifetime of the devices with no impact on the initial performance.