This work introduces SENSOTERIC, a multi-partner project that aims at leveraging the properties of emerging Reconfigurable Field Effect Transistors (RFETs) to develop a sensor platform. RFETs will be used for a generic sensor interface and for a dedicated transducer element. In the first case, our goal is to develop an analog front-end interface that can be tuned at runtime to adapt to different environmental conditions and be used in a broad spectrum of applications. This feature shall be enabled by the polarity-control and negative differential resistance characteristics of the reconfigurable devices employed, that are co-integrable on industrial CMOS processes such as 22 nm FDSOI. In the second case, we want to exploit the intrinsic nature of these doping-free devices to yield better 1/f noise performances when compared to classic CMOS transducers. Moreover, the presence of un-gated areas on top of the channel of these devices makes them the perfect candidates to be functionalized. In this early-stage overview of the project, we will introduce the key features and the vision that make SENSOTERIC a unique contribution towards smart sensing solutions in environmental monitoring and healthcare.

Reconfigurable field-effect transistors (RFETs), allowing dynamic run-time switching between n- and p-type operation, are already considered a viable CMOS add-on technology to enable adaptive computing concepts. Beyond that, exploiting the multi-gate architecture of RFETs can also be beneficial for analog circuits but has been less explored. Here, we experimentally demonstrate an adaptive current mirror based on Ge RFETs with the ability of electrostatic compensation of device-to-device variations, enabling an ideal current mirror that can even be switched between n- and p-type operation. Furthermore, the IOUT/IIN-ratio can be adjusted electrostatically without the need for additional devices. This enhances the abilities of traditional current mirrors that are not adjustable after manufacturing without the need for complex additional circuitry.

While a number of measures have been proposed to protect the integrity of COS hardware, there are some inherent limitations from classical CMOS methods. Those already existing security methods, like logic locking can be improved with emerging technologies such as Reconfigurable Field Effect Transistors (RFETs). RFETs are a special type of doping-free, Schottky transistors which can work as a PFET or NFET as a function of biasing across its gates. In the present study we developed standard cell layouts for dynamic reconfigurable security cells based on three-independent-gated RFETs (TIG-RFETs). They layouts are compatible to an industrial 22nm FDSOI technology, feature the minimum pitch of the baseline technology, and obey all design rules necessary for co-integration. The designs enable a fair area comparison for RFET based digital application for the first time. Based on the sizing constraints from the layouts, a TCAD model of such a TIG-RFET is developed in Sentaurus TCAD to illustrate two biasing schemes for the application of TIGRFETs in this platform: reconfigurability with individual body-bias per transistor and reconfigurability at globally fixed body-bias. Due to the different operation options three variants of reconfigurable 2-XOR-XNOR and 2-NAND-NOR logic cells exhibiting different level of utility are designed. While the smallest dynamic 2-NAND-NOR gate needs roughly double the area of a CMOS 2-NAND gate from the reference library, the smallest 2-XOR-XNOR gate is only 20% larger than a CMOS 2-XOR. To quantify the area overhead for hardware security applications we calculated the number of logic locking gates that can be added per area overhead for a given circuit, here the ISCAS-85 C6288 benchmark circuit, as an example. Dynamic replacement based logic locking with TIG-RFETs shows to allow up to double the number of keys compared to classical CMOS logic locking per area overhead. Therefore, this work allows a realistic view on the application of RFETs in hardware security and its co-integrability along with some design constraints from an industrial PDK.

Power attacks are effective side-channel attacks (SCAs) that exploit weaknesses in the physical implementation of a cryptographic circuit to extract its secret information like encryption key. In recent years, emerging technologies have unlocked new possibilities in designing effective SCA countermeasures with less overhead. Reconfigurable Field-Effect Transistors (RFETs) are a type of beyond-CMOS technology that can be configured at run-time to act as an NFET or PFET transistor and provide two or more independent gates. These features make RFETs potent candidates for implementing hardware security techniques like logic locking and SCA countermeasures. In this paper, we propose REDCAP, a method to add randomness to the power traces of a circuit, employing compact reconfigurable RFET-based gates to make the design resilient against power SCAs. First, we explain the construction and control of reconfigurable blocks with isofunctional configurations inside the circuit. Then, we provide an algorithm to efficiently compose the reconfigurable blocks with other circuit parts to minimize the overhead and enable designers to determine the granularity of the reconfiguration. To evaluate our approach, we performed a Correlation Power Attack (CPA) on the S-box of the Piccolo and PRESENT, two lightweight cryptographic circuits, and the results show that REDCAP can highly enhance the resilience of the circuit against power SCAs.

This multi-partner-project contribution introduces the midway results of the Horizon 2020 FVLLMONTI project. In this project we develop a new and ultra-efficient class of ANN accelerators, the neural network compute cube$(N^{2}C^{2})$, which is specifically designed to execute complex machine learning tasks in a 3D technology, in order to provide the high computing power and ultra-high efficiency needed for future edgeAI applications. We showcase its effectiveness by targeting the challenging class of Transformer ANNs, tailored for Automatic Speech Recognition and Machine Translation, the two fundamental components of speech-to-speech translation. To gain the full benefit of the accelerator design, we develop disruptive vertical transistor technologies and execute design-technology-co-optimization (DTCO) loops from single device, to cell and compute cube level. Further, a hardware-software-co-optimization is executed, e.g. by compressing the executed speech recognition and translation models for energy efficient executing without substantial loss in precision.

Side-Channel Attacks (SCAs), which are always considered a severe threat to the security of the cryptographic circuits, today can also be employed to extract IP secrets and neural network models. Hence, developing novel security solutions at different design levels is crucial. In this paper, we explore recent countermeasures at the circuit, algorithmic, and microarchitecture levels. First, we explain how Reconfigurable Field-Effect Transistor (RFET), as a beyond CMOS technology, enables us to provide both IP and data protection against SCAs at the circuit level. Second, we investigate an automated method for generating masked circuits as an algorithmic solution, and then we review machine learning-based SCA detection mechanisms at the microarchitecture level. Finally, we discuss emerging threats of SCAs from the industrial point of view.

Reconfigurable transistors are a new emerging type of device, which offer the promise to improve the resistance of electronic components against know-how theft. In order to enable a product development of such an emerging device, a cross-layer design enablement strategy is needed, as emerging technologies are not necessarily compatible withstandard tools used in the industry. In ‘CirroStrato’, we aim on the development of such a complete flow enabling CMOS co-integration of reconfigurable transistors, ranging from process adjustments, device modeling, library characterization, physical and logical synthesis up towards sophisticated hardware security tests. In this multi-partner-project (MPP) paper, our aim is to elucidate the overall design enablement flow, as well as current research challenges on the individual stages.

The field of computer hardware stands at the verge of a revolution driven by recent breakthroughs in emerging nanodevices. “Nano Security” is a new Priority Program recently approved by DFG, the German Research Council. This initial-stage project initiative at the crossroads of nano-electronics and hardware-oriented security includes 11 projects with a total of 23 Principal Investigators from 18 German institutions. It considers the interplay between security and nano-electronics, focusing on a dichotomy which emerging nano-devices (and their architectural implications) have on system security. The projects within the Priority Program consider both: potential security threats and vulnerabilities stemming from novel nano-electronics, and innovative approaches to establishing and improving system security based on nano-electronics. This paper provides an overview of the Priority Program's overall philosophy and discusses the scientific objectives of its individual projects.

The traditional Von-Neumann architecture is reaching its limits and finding it difficult to cope up with the ever-increasing demands of modern workloads like artificial intelligence. This demand has fueled the search of technologies that can mimic human brain to efficiently combine both memory and computation within a single device. In this work, we present the state-of-the-art research in the domain of computation-in-memory. In particular, we take a look at memristors and its widespread application in neuromorphic computation. We introduce ReRAMs in terms of their novel computing paradigms and present ReRAM-specific design flows. We address the various circuit opportunities and challenges related to reliability and fault tolerance associated with them. Another high-potential candidate to leverage memory and computation from a single device is Ferroelectric Field-effect Transistor (FeFET). Here we present a co-integration of such FeFETs with another emerging nanotechnology concept, called Reconfigurable Field Effect Transistor (RFET) and discuss the impact of the higher amount of states provided by this combination.

An early evaluation in terms of circuit design is essential in order to assess the feasibility and practicability aspects for emerging nanotechnologies. Reconfigurable nanotechnologies, such as silicon or germanium nanowire-based reconfigurable field-effect transistors, hold great promise as suitable primitives for enabling multiple functionalities per computational unit. However, contemporary CMOS circuit designs when applied directly with this emerging nanotechnology often result in suboptimal designs. For example, 31% and 71% larger area was obtained for our two exemplary designs. Hence, new approaches delivering tailored circuit designs are needed to truly tap the exciting feature set of these reconfigurable nanotechnologies. To this effect, we propose six functionally enhanced logic gates based on a reconfigurable nanowire technology and employ these logic gates in efficient circuit designs. We carry out a detailed comparative study for a reconfigurable multifunctional circuit, which shows better normalized circuit delay (20.14%), area (32.40%), and activity as the power metric (40%) while exhibiting similar functionality as compared with the CMOS reference design. We further propose a novel design for a 1-bit arithmetic logic unit-based on silicon nanowire reconfigurable FETs with the area, normalized circuit delay, and activity gains of 30%, 34%, and 36%, respectively, as compared with the contemporary CMOS version.

Silicon Nanowire (SiNW) based reconfigurable field-effect transistors (RFETs) provide an additional gate terminal called the program gate which gives the freedom of programming p-type or n-type functionality for the same device at runtime. This enables the circuit designers to pack more functionality per computational unit. This saves processing costs as only one device type is required, and no doping and associated lithography steps are needed for this technology. In this paper, we present a complete design flow including both logic and physical synthesis for circuits based on SiNW RFETs. We propose layouts of logic gates, Liberty and LEF (Library Exchange Format) files to enable further research in the domain of these novel, functionally enhanced transistors. We show that in the first of its kind comparison, for these fully symmetrical reconfigurable transistors, the area after placement and routing for SiNW based circuits is 17% more than that of CMOS for MCNC benchmarks. Further, we discuss areas of improvement for obtaining better area results from the SiNW based RFETs from a fabrication and technology point of view. The future use of self-aligned techniques to structure two independent gates within a smaller pitch holds the promise of substantial area reduction.

Silicon nanowire reconfigurable field effect transistors (SiNW RFETs) abolish the physical separation of n-type and p-type transistors by taking up both roles in a configurable way within a doping-free technology. However, the potential of transistor-level reconfigurability has not been demonstrated in larger circuits, so far. In this paper, we present first steps to a new compact and efficient design of combinational circuits by employing transistor-level reconfiguration. We contribute new basic gates realized with silicon nanowires, such as 2/3-XOR and MUX gates. Exemplifying our approach with 4-bit, 8-bit and 16-bit conditional carry adders, we were able to reduce the number of transistors to almost one half. With our current case study we show that SiNW technology can reduce the required chip area by 16 despite larger size of the individual transistor, and improve circuit speed by 26%.

Reconfigurable fine-grain electronics target an increase in the number of integrated logic functions per chip by enhancing the functionality at the device level and by implementing a compact and technologically simple hardware platform. Here we study a promising realization approach by employing reconfigurable nanowire transistors (RFETs) as the multifunctional building-blocks to be integrated therein. RFETs merge the electrical characteristics of unipolar n- and p- type FETs into a single universal device. The switch comprises four terminals, where three of them act as the conventional FET electrodes and the fourth acts as an electric select signal to dynamically program the desired switch type. The transistor consists of two independent charge carrier injection valves as represented by two gated Schottky junctions integrated within an intrinsic silicon nanowire. Radial compressive strain applied to the channel is used as a scalable method to adjust n- and p-FET currents to each other, thereby enabling complementary logic circuits. Simple but relevant examples for the reconfiguration of complete gates will be given, demonstrating the potential of this technology.