Abraham Akinin

dblp:144/6140 · DBLP profile ↗
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2ranked-venue papers
0as first author
1since 2021 · last 2023
0000-0002-6761-8425ORCID · verified

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 since 2021Applied, interdisciplinary, general and emerging computing · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Integrated circuit design · 50% Hardware accelerators and domain-specific architectures · 50%
Computer networks
1 paper
Wireless networking · 100%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Integrated circuit design
analog and mixed-signal circuits
0.312017
Silicon-Integrated High-Density Electrocortical Interfaces · Proc. IEEE 2017
Hardware accelerators and domain-specific architectures › bioinformatics accelerator
biomedical accelerator
0.312017
Silicon-Integrated High-Density Electrocortical Interfaces · Proc. IEEE 2017
Wireless networking
wireless power transfer
0.112017
Silicon-Integrated High-Density Electrocortical Interfaces · Proc. IEEE 2017

Methods — techniques the papers use, named apart from their topics

wireless communication circuit design · 0.6modular system design · 0.6
YearPublicationVenuePosition
2023 A Low-Noise 0.001Hz-lkHz Sample-Level Duty-Cycling Neural Recording System-on-Chip
abstract
Multiscale dynamics of neural and metabolic interactions implicated in disease states call for precision electrophysiology to resolve a variety of biopotential signals across the body that cover a wide range of frequencies, from the mHz-range electrogastrogram (EGG) to the kHz-range electroneurogram (ENG). Currently available integrated systems for unobtrusive and minimally invasive electrophysiology suffer from tradeoffs between bandwidth coverage, noise floor, power consumption, and input impedance, which limits their detection range and accuracy. Here we present a 16-channel wide-band ultra-low-noise neural recording system-on-chip fabricated in 65nm CMOS for chronic use in mobile healthcare settings that covers 0.001 Hz to 1 kHz bandwidth through sample-level duty-cycling. Each channel consists of a delta-sigma analog-to-digital converter (ADC) achieving$\mathbf{1.0}\ \mu \mathbf{V}_{rms}$input-referred noise over 1 Hz - 1 kHz bandwidth with a Noise Efficiency Factor (NEF) of 2.93 in continuous operation mode, while power duty-cycling of the biasing and clocks maintains consistent low input-referred noise levels down to 0.001 Hz sampling rates at$\mathbf{435}\ \mathbf{M}\Omega$input impedance. In vivo recordings from the chip interfacing to electrodes mounted on the forehead resolving slow-wave electroencephalogram (EEG) biopotentials demonstrate proof-of-concept functionality.
Jiajia Wu 0008, Abraham Akinin, Min Lee, Akshay Paul, Yongjae Park, Preston Fowler, Seong-Jin Kim, Patrick P. Mercier, Gert Cauwenberghs
ISCAS2
2017 Silicon-Integrated High-Density Electrocortical Interfaces
abstract
Recent demand and initiatives in brain research have driven significant interest toward developing chronically implantable neural interface systems with high spatiotemporal resolution and spatial coverage extending to the whole brain. Electroencephalography-based systems are noninvasive and cost efficient in monitoring neural activity across the brain, but suffer from fundamental limitations in spatiotemporal resolution. On the other hand, neural spike and local field potential (LFP) monitoring with penetrating electrodes offer higher resolution, but are highly invasive and inadequate for long-term use in humans due to unreliability in long-term data recording and risk for infection and inflammation. Alternatively, electrocorticography (ECoG) promises a minimally invasive, chronically implantable neural interface with resolution and spatial coverage capabilities that, with future technology scaling, may meet the needs of recently proposed brain initiatives. In this paper, we discuss the challenges and state-of-the-art technologies that are enabling next-generation fully implantable high-density ECoG interfaces, including details on electrodes, data acquisition front-ends, stimulation drivers, and circuits and antennas for wireless communications and power delivery. Along with state-of-the-art implantable ECoG interface systems, we introduce a modular ECoG system concept based on a fully encapsulated neural interfacing acquisition chip (ENIAC). Multiple ENIACs can be placed across the cortical surface, enabling dense coverage over wide area with high spatiotemporal resolution. The circuit and system level details of ENIAC are presented, along with measurement results.
Sohmyung Ha, Abraham Akinin, Jiwoong Park, Chul Kim, Hui Wang 0023, Christoph Maier, Patrick P. Mercier, Gert Cauwenberghs
Proc. IEEE2