In the era of intelligent systems, the real-time perception task becomes essential to enable emerging applications, such as assistive technology for visually impaired individuals, autonomous navigation in robotics, mission control, and smart agriculture, among others. As artificial intelligence (AI) continues to advance, deploying lightweight AI models on low-power Internet of Things (IoT) devices remains a critical challenge due to computational and power limitations. The goal of this research is to investigate and develop a system model of real-time AI-driven perception tasks for low-power IoT devices. Therefore, a system model is designed to solve the perception task in real-time. The significance of this research lies in enabling lightweight AI models to operate efficiently on resource-constrained devices, making obstacle detection accessible and cost-effective for IoT applications. In particular, this work investigates an obstacle detection system as a perception task by leveraging a You Only Look Once (YOLO)-based machine learning (ML) model on a low-cost and low-power computing platform such as the Raspberry Pi 4B. The results demonstrate a promising average accuracy level of 84.8% with a maximum of 95.6%, while the end-to-end post-processing time is 1.7ms to complete the considered perception task.

Here, we present a computational photography-based biometric scanner to capture deep wrist vascular arcades using multi-zone NIR LED banks and multi-exposure HDR per each illumination zone, achieving exceptional pseudo-color imaging of the wrist volume, in addition to other anatomical features such as high-resolution skin textures. Using NIR illumination on dorsal, lateral, and ventral positions, deeper vascular structures are encoded in red and green, and superficial textures and veins in blue. As an internal biometric, this modality inherently provides stronger security and privacy. Implemented on an NVIDIA Jetson platform, we further leverage secure computation using ARM TrustZone isolation, encrypted data storage, and secure boot functionalities. Experimental results validate the effectiveness and computational efficiency of the proposed system, demonstrating its potential for secure, real-time, and privacy-preserving biometric applications.

Operational resiliency becomes a key requirement to prevent critical recall of distributed energy resources (DER) in Cyber-Physical Energy Systems (CPES). Thus, CPES requires methods and metrics to observe and understand the potential faults of unwanted cyber-physical events. This paper introduces a new Native-AI-driven predictive maintenance framework to ensure the operational resiliency of CPES. First, a system model is designed to capture operational states such as normal, service mode, and faults by observing the operational behavior of DERs. Second, a predictive maintenance framework is proposed and developed by introducing a dual-method feature selection mechanism while the features of critical recall states are selected by tailored Gini and permutation-based importance metrics. Third, the predictive model is designed by leveraging tree-based models that utilize cyclical temporal encoding and lag features, while a Long Short-Term Memory (LSTM) family models employ sequence learning with normalized temporal and angular representations. Finally, the proposed framework can achieve up to 99.97% Critical Recall detection accuracy with an average of 82.5%. As a result, this work advances AI-driven predictive maintenance by reducing downtime by 15–30% in simulated scenarios.

Given the popularity and importance of biometric personal identification, new modalities continue to be explored by the research community, including those based on the infrared scans of the target tissues. This paper presents a study of functional near-infrared spectroscopy (fNIRS) as a potential biometric modality. We assess the subject-specificity of the fNIRS’s functional and structural signatures using a multichannel fNIRS dataset collected over the forehead during various motor tasks and rest states. We detail our preprocessing, feature extraction (with Uniform Manifold Approximation and Projection), and feature selection (with permutation feature importance). Using cosine similarity matching between enrollment and validation features from an average of four mental actions, we obtained an area under the ROC curve (AUC) of 0.86. We also compare the efficacy of various classifiers, such as tree-based, neural network-based, and gradient-boosting-based models. An ensemble classifier improved the verification accuracy and AUC over the test data set to 96% and 0.99, respectively.

Evident by the Federal Communications Commission’s (FCC) incorporation of a light leasing approach, high utilization of the Citizens Broadband Radio Service (CBRS) spectrum can be achieved by the commercial Priority Access License (PAL) operators sharing resources with unlicensed General Authorized Access (GAA) users. However, proper integration of PAL operators and GAA users into this new three-tiered CBRS spectrum sharing market is an open issue. This work introduces a collaborative GAA-clustered framework to facilitate such integration. We propose GAA users form multiple distinct geographical clusters and utilize the CBRS spectrum collaboratively rather than through individual access requests. Each cluster will nominate a central entity called the GAA leader, who will directly communicate with the PAL operators regarding CBRS spectrum access and set up the necessary PAL-GAA connections. Such direct communication will reduce the messaging overhead between the central CBRS Spectrum Access System (SAS) and the users across PAL and GAA levels, providing a reliable and convenient spectrum-sharing platform. Here, we propose a novel leader selection algorithm (LSA) that uses a GAA user’s network density and perceived signal strength to assign a Leader Evaluation Score (LES) to evaluate and nominate the GAA user with the highest score as the cluster leader.

The Federal Communications Commission (FCC) recently deployed the Citizens Broadband Radio Service (CBRS), a three-tiered spectrum-sharing approach that allows incumbent federal users to share the 3,550-3,700 MHz band with commercial users. In addition, the FCC also aims to encourage licensed providers, called the Priority Access License (PAL), to lease/share their licensed spectrum with unlicensed users, named the General Authorized Access (GAA), for a limited duration, by adopting a light leasing approach. In this paper, we aim to facilitate PAL-GAA collaborative spectrum access by proposing a novel clustered framework where the GAA users are grouped into multiple distinct geographical clusters and request access to the CBRS spectrum resources through the clusters collaboratively rather than individually. This process reduces the control messaging overhead between the CBRS controller and licensed and unlicensed entities, providing a convenient platform for licensed spectrum sharing. Also, submitting aggregated requests from multiple users rather than individuals will allow PAL operators to estimate the data traffic that their network may experience due to sharing. Later, PALs can make arrangements to allocate appropriate spectrum resources for sharing to the GAA layer. Finally, to encourage PALs to share, we also propose a government incentive model where PALs are allotted additional bandwidth for a limited span to be used as an extension to their licensed spectrum based on their level of sharing.

Intellectual Property (IP) includes ideas, innovations, methodologies, works of authorship (viz., literary and artistic works), emblems, brands, images, etc. This property is intangible since it is pertinent to the human intellect. Therefore, IP entities are indisputably vulnerable to infringements and modifications without the owner’s consent. IP protection regulations have been deployed and are still in practice, including patents, copyrights, contracts, trademarks, trade secrets, etc., to address these challenges. Unfortunately, these protections are insufficient to keep IP entities from being changed or stolen without permission. As for this, some IPs require hardware IP protection mechanisms, and others require software IP protection techniques. To secure these IPs, researchers have explored the domain of Intellectual Property Protection (IPP) using different approaches. In this paper, we discuss the existing IP rights and concurrent breakthroughs in the field of IPP research; provide discussions on hardware IP and software IP attacks and defense techniques; summarize different applications of IP protection; and lastly, identify the challenges and future research prospects in hardware and software IP security.

One of the essential elements of computing is the memory element. Flip-flops form an integral part of a System-on-Chip (SoC) and consume most of the area on the die. To meet the high-speed performance demands by the data-intensive applications such as artificial intelligence, cloud computing, and machine learning, we propose to integrate memory with the logic to get built-in memory Logic circuits that operate based on the crosstalk computing logic. These circuits are called Crosstalk Built-in Memory Logic (CBML) circuits, which exploit the detrimental interconnect crosstalk and astutely turn this unwanted effect into a computing principle with embedded memory. By virtue of our novel CBML circuit technique, the logic is computed, and the result is stored intrinsically within these complex circuits. The stored values will be retained irrespective of the change in input until the next logic evaluation cycle. This neoteric embedding of memory in logic provides high-speed operation with a reduced number of transistors. In this article, we have manifested the built-in memory feature of the complex CBML circuits using 16 nanometer (nm) PTM models in HSPICE. Benchmarking is performed by comparing with the equivalent static CMOS circuits to compare the number of transistors, power, and performance. It is observed that the number of transistors consumed by CBML 4-bit Full-Adder (the key element prevalent in Arithmetic circuits, e.g., ALU, Counters) is up to 46% less, and performance is improved by 27% over the equivalent CMOS circuits. This circuit serves as an example of a large-scale CBML circuit. Also, the performance improvement achieved by other circuits such as 3-input AND and the CARRY logic is up to 60% along with a 40% reduction in the number of transistors. CBML circuits have the potential to pave the way for special high-speed macros with specifically engineered structures.

Unmanned Aerial Vehicle (UAV) based delivery networks have emerged as a promising mode of parcel delivery owing to their efficient and cost-effective operations. In this paper, we propose a novel techno-economic framework to facilitate multi-operator UAV delivery networks in Beyond Visual Line of Sight (BVLoS) communications. The proposed model aims at partitioning a large delivery zone into several small cells, each receiving separate licensing to carry out UAV operations. A controlling entity called UAV Traffic Controller (UTC) governs each cell and manages all UAV movements within the cell while adhering to the Federal Aviation Authority’s regulations. A UTC also authenticates all UAVs running within its airspace and secures delivery service providers’ and customers’ privacy.

The functionality of polymorphic circuits can be altered using a control variable. Owing to the multifunctional embodiment in polymorphic circuits, they are helpful to reconfigure circuit behavior from the gate level to the system level, either on the fly or off-line. The polymorphic circuit approaches available in the literature are either based on custom nonlinear circuit designs or special emerging devices, such as ambipolar FET and configurable magnetic devices. While some of these approaches are inefficient in performance, the other approaches involve exotic devices. We have proposed a novel polymorphic circuit design approach based on crosstalk (CT) computing, where we leverage deterministic signal interference between nanometal lines for logic computation and reconfiguration. In this article, we elaborate upon the polymorphic circuit design in CT computing through mathematical formulation, which conveys the rationale to generalize and achieve a wide variety of polymorphic circuits, and then demonstrate a comprehensive list of polymorphic circuit designs. In addition, all circuits are characterized and benchmarked against CMOS circuit implementations to gauge the benefits. Finally, we compare the CT polymorphic circuit approach with other approaches in the literature and highlight its unique features and limitations. The ability to design a wide range of polymorphic logic circuits (basic and complex logics) compact in design and minimal in transistor count is unique to CT computing, which leads to benefits in the circuit power, performance, and area (PPA). Our circuit designs, simulation, and PPA characterization results show that the polymorphic CT circuits provide$3\times $improvement in transistor count,$2\times $improvement in switching energy, and$1.5\times $improvement in speed for polymorphic logic circuits. In the best-case, the transistor count reduction is$5\times $.

Cell tower locations are not publicly available due to business interests of wireless providers. Very often wireless providers provide exaggerated coverage maps that may mislead the public. In addition to providing a neutral check on the coverage maps, prediction of cell tower locations hosting multiple operators’ access nodes could also be helpful in disaster communications and public safety in general. The localization of the disaster-affected towers can be very conducive to respond and reach to the victims. Further, victims’ devices could utilize this knowledge to initiate device-to-device (D2D) or unmanned aerial vehicular (UAV) communications as alternatives to the damaged cellular infrastructure. Publicly available crowdsourced cell (base station) locations and FCC’s sites can be used to predict the cell tower/site locations in the United States. In this work, we utilized a weighted k-means algorithm to predict cell tower locations from OpenCellid crowdsourced dataset and implemented a mapping algorithm to locate nearest physical towers. We map the predicted towers to two different sources of physical towers. Our comparison shows a significant accuracy in predicting tower locations regardless of sources of physical towers. The technique can be used to predict the tower locations in other countries as well.

Primary-secondary spectrum sharing is limited in terms of design space, and may not be sufficient to meet the ever-increasing demand of connectivity and high signal quality. The next step to increase spectrum sharing efficiency is to design markets where sharing takes place among primary providers rather than leaving it to the limited case where the primary licensee is idle. Attaining contractual spectrum sharing among primary providers, a.k.a. co-primary or inter-provider sharing, involves additional costs for the users, e.g., roaming fee. Co-primary spectrum sharing without additional charge to the users poses two major challenges: a) regulatory approaches must be introduced to incentivize providers to share spectrum resources, and b) small providers in co-primary spectrum sharing markets may freeride on large providers' networks as the customers of the small providers may be using the spectrum and infrastructure resources of large providers. Such freeriding opportunities must be minimized to realize the benefits of primary-level sharing. We consider a subsidy-based spectrum sharing (SBSS) market to facilitate co-primary spectrum sharing where providers are explicitly incentivized to share spectrum resources. We focus on minimizing freeriding in SBSS markets and introduce a game-theoretic model to regulate the freeriding. We use the model to explore operational regimes with minimal freeriding.

As 2-D CMOS reaches its fundamental scaling limits due to device, manufacturing, and interconnect bottleneck related constraints at the nanoscale, migration to 3-D provides a possible alternative to continue technology scaling in future. Toward that goal, several 3-D integration approaches with multi-die, multichip, and sequential layers stacking are pursued. However, these approaches only show incremental density benefits and exhibit new challenges, such as lack of thermal management, increasing cost, and reliability issues. In contrast to these, we proposed a radically different fabric concept, called stacked horizontal nanowire-based 3-D CMOS (SN3D), on a single die that can offer a paradigm shift in technology scaling as well as design. Using prefabricated and doped stacked horizontal nanowires as fundamental building blocks, the fabric is assembled using architected connectivity and insulation features. Innovations in circuit style for mapping to SN3D's physical framework, and bottom-up material filling-based manufacturing techniques are also central to our approach. In this paper, we detail, fabric's core constructs, logic circuits implementation in SN3D fabric, benchmarking methodology and results, and finally the manufacturing aspects. Our circuit analysis reveals tremendous benefits; for a 4-bit full adder design, SN3D shows 11×, 19%, 18%, and 6.7x, 8.69%, 9% benefits over state-of-art 2-D CMOS and transistor-level monolithic 3-D in terms of density, power, and performance, respectively. In addition, our step-by-step TCAD emulation of manufacturing flow establishes feasibility. If realized, the SN3D fabric can be transformative for the semiconductor industry.

Wireless devices with diverse capabilities are ubiquitous and will continue to flourish for the next foreseeable future. With cellular connectivity, each devicd is capable to utilize more necessary services. However, in some cases (e.g., public safety and disaster recovery) cellular connectivity may become unavailable. In these situations, device-to-device (D2D) communication can contribute to maintain connectivity as well as providing other services in terms of service sharing (e.g., SMS, Internet, camera) available in individual devices. This paper describes an approach where users can share wireless services with other users in a seamless manner. We develop a smart phone application, D2DMesh, for service sharing in a D2D manner. By using D2DMesh, users can get more work done via sharing, increase the spectrum utilization, create their own private networks without a centralized infrastructure and offload network traffic to a less congested network path. Our approach is platform-independent and is entirely implemented in user space. It allows sharing of services among neighboring devices over multiple hops without any help from the device vendors. We present results from initial experiments and show the effects of various important parameters on the performance of D2D service sharing.

Graphene is an emerging nanomaterial believed to be a potential candidate for post-Si nanoelectronics due to its exotic properties. Recently, a new graphene nanoribbon crossbar (xGNR) device was proposed which exhibits negative differential resistance (NDR). In this article, a multistate memory design is presented that can store multiple bits in a single cell enabled by this xGNR device, called graphene nanoribbon tunneling random access memory (GNTRAM). An approach to increase the number of bits per cell is explored alternative to physical scaling to overcome CMOS SRAM limitations. A comprehensive design for quaternary GNTRAM is presented as a baseline, implemented with a heterogeneous integration between graphene and CMOS. Sources of leakage and approaches to mitigate them are investigated. This design is extensively benchmarked against 16nm CMOS SRAMs and 3T DRAM. The proposed quaternary cell shows up to 2.27× density benefit versus 16nm CMOS SRAMs and 1.8× versus 3T DRAM. It has comparable read performance and is power efficient up to 1.32× during active period and 818× during standby against high-performance SRAMs. Multistate GNTRAM has the potential to realize high-density low-power nanoscale embedded memories. Further improvements may be possible by using graphene more extensively, as graphene transistors become available in the future.

Maintaining benefits of CMOS technology scaling is becoming challenging, primarily due to increased manufacturing complexities and unwanted passive power dissipations. This is particularly challenging in SRAM, where manufacturing precision and leakage power control are critical issues. To alleviate these challenges, we proposed a novel volatile memory alternative to SRAM called nanowire volatile RAM (NWRAM). Due to NWRAM's regular grid-based layout and innovative circuit style, manufacturing complexities are reduced and, at the same time, considerable benefits are attained in terms of performance and leakage power reduction. In this article we elaborate NWRAM's circuit aspects and manufacturability, and quantify benefits at 16nm technology node through simulation against state-of-the-art 6T-SRAM and gridded 8T-SRAM designs. Our results show that when lower bounds in design rules are considered, 10T-NWRAM's read and write time are 1.38x and 2x faster, and the leakage power is 14x better in comparison to high-performance 6T-SRAM. Similarly the 10T-NWRAM achieves 1.3x and 1.9x read and write performance, and 35x leakage power improvements compared to high-performance 8T-SRAM. 10T-NWRAM's density is comparable to 6T-SRAM and 8T-SRAM for lower bounds, but exhibits higher active power in similar comparisons. This article details all benchmarking results and provides thorough analysis of NWRAM's evaluations.