We present PacketMill, a system for optimizing software packet processing, which (i) introduces a new model to efficiently manage packet metadata and (ii) employs code-optimization techniques to better utilize commodity hardware. PacketMill grinds the whole packet processing stack, from the high-level network function configuration file to the low-level userspace network (specifically DPDK) drivers, to mitigate inefficiencies and produce a customized binary for a given network function. Our evaluation results show that PacketMill increases throughput (up to 36.4 Gbps -- 70%) & reduces latency (up to 101 us -- 28%) and enables nontrivial packet processing (e.g., router) at ~100 Gbps, when new packets arrive >10× faster than main memory access times, while using only one processing core.

In modern (Intel) processors, Last Level Cache (LLC) is divided into multiple slices and an undocumented hashing algorithm (aka Complex Addressing) maps different parts of memory address space among these slices to increase the effective memory bandwidth. After a careful study of Intel's Complex Addressing, we introduce a slice-aware memory management scheme, wherein frequently used data can be accessed faster via the LLC. Using our proposed scheme, we show that a key-value store can potentially improve its average performance ~12.2% and ~11.4% for 100% & 95% GET workloads, respectively. Furthermore, we propose CacheDirector, a network I/O solution which extends Direct Data I/O (DDIO) and places the packet's header in the slice of the LLC that is closest to the relevant processing core. We implemented CacheDirector as an extension to DPDK and evaluated our proposed solution for latency-critical applications in Network Function Virtualization (NFV) systems. Evaluation results show that CacheDirector makes packet processing faster by reducing tail latencies (90-99th percentiles) by up to 119 μs (~21.5%) for optimized NFV service chains that are running at 100 Gbps. Finally, we analyze the effectiveness of slice-aware memory management to realize cache isolation.

The rapid growth of data and high-dependency of industries on using data put lots of focus on the computing facilities.Increasing the efficiency and re-architecting the underlying infrastructure of datacenters, has become a major priority.The total cost of owning and running a datacenter (DC) is affected by many parameters, which until recently were ignored as their impact on the business economy was negligible.However, that is not the case anymore, as in the new era of digital economy every penny counts.The market is too aggressive to ignore anything.Hence, the economic efficiency becomes vital for cloud infrastructure providers despite their size.This article presents a framework to assess cloud infrastructure economic efficiency, taking into account three main aspects: application profiling, hardware dimensioning and total cost of ownership (TCO).Moreover, it presents a cost study of deploying the emerging concept of disaggregated hardware architecture in DCs based on the proposed framework.The study considers all the major cost categories incurred during the DC lifetime in terms of both capital and operational expenditures.A thorough cost comparison between a DC running on a disaggregated hardware architecture with one running on a traditional server-based hardware architecture is presented.The study demonstrates the evolution of the yearly cost over DC lifetime as well as a sensitivity analysis, allowing to understand how to minimize the cost of running cloud.Results show that, lifecycle management cost is one of the main differentiators between two technologies.Moreover, it is shown that in the presence of heterogeneous workloads, having a DC based on a fully disaggregated hardware brings high savings (more than 40% depending on the applications) compared to the traditional hardware architectures independent of the hardware set-up.