Demo Data from VLDB 2026 / reviewers in the wild / expert
Thomas Shull
dblp:145/1026
· DBLP profile ↗
11ranked-venue papers
4as first author
2since 2021 · last 2021
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 8 · 3 first-author · 2 since 2021Software engineering, systems software and programming languages · 6 · 2 first-author · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
6 papers |
Memory systems · 45% Processor architecture and microarchitecture · 39% Hardware accelerators and domain-specific architectures · 10% | |
| Software engineering, system software, and programming languages
5 papers |
Runtime systems and virtual machines · 61% Compilers and program optimization · 23% Operating systems · 14% | |
| Network and information security
1 paper |
Hardware security and side channels · 100% |
Topics — the 18 heaviest of 21, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Memory systems
non-volatile memory |
1.3 | 3 | 2021 | Execution Dependence Extension (EDE): ISA Support for Eliminating Fences · ISCA 2021 P-INSPECT: Architectural Support for Programmable Non-Volatile Memory Frameworks · MICRO 2020 AutoPersist: an easy-to-use Java NVM framework based on reachability · PLDI 2019 |
Runtime systems and virtual machines › virtual machine implementation
javascript engine |
0.9 | 3 | 2019 | Reusable inline caching for JavaScript performance · PLDI 2019 NoMap: Speeding-Up JavaScript Using Hardware Transactional Memory · HPCA 2019 Improving JavaScript performance by deconstructing the type system · PLDI 2014 |
Runtime systems and virtual machines › dynamic compilation
just-in-time compilation |
0.8 | 2 | 2019 | Reusable inline caching for JavaScript performance · PLDI 2019 NoMap: Speeding-Up JavaScript Using Hardware Transactional Memory · HPCA 2019 |
Processor architecture and microarchitecture
instruction set architecture |
0.5 | 1 | 2021 | Execution Dependence Extension (EDE): ISA Support for Eliminating Fences · ISCA 2021 |
Processor architecture and microarchitecture › memory system microarchitecture
memory ordering |
0.5 | 1 | 2021 | Execution Dependence Extension (EDE): ISA Support for Eliminating Fences · ISCA 2021 |
Memory systems › non-volatile memory
persist ordering |
0.5 | 1 | 2021 | Execution Dependence Extension (EDE): ISA Support for Eliminating Fences · ISCA 2021 |
Compilers and program optimization › dynamic optimization
inline caching |
0.5 | 2 | 2019 | Reusable inline caching for JavaScript performance · PLDI 2019 ShortCut: Architectural Support for Fast Object Access in Scripting Languages · ISCA 2017 |
Operating systems › resource management
memory management |
0.4 | 1 | 2019 | AutoPersist: an easy-to-use Java NVM framework based on reachability · PLDI 2019 |
Hardware security and side channels
cache replacement policy |
0.3 | 1 | 2017 | Secure Hierarchy-Aware Cache Replacement Policy (SHARP): Defending Against Cache-Based Side Channel Attacks · ISCA 2017 |
Hardware security and side channels › side-channel attack
cache side-channel attacks |
0.3 | 1 | 2017 | Secure Hierarchy-Aware Cache Replacement Policy (SHARP): Defending Against Cache-Based Side Channel Attacks · ISCA 2017 |
Compilers and program optimization › dynamic optimization
dynamic language optimization |
0.2 | 1 | 2014 | Improving JavaScript performance by deconstructing the type system · PLDI 2014 |
Processor architecture and microarchitecture › out-of-order execution
issue queue |
0.1 | 1 | 2021 | Execution Dependence Extension (EDE): ISA Support for Eliminating Fences · ISCA 2021 |
Processor architecture and microarchitecture › out-of-order execution
out-of-order pipeline |
0.1 | 1 | 2021 | Execution Dependence Extension (EDE): ISA Support for Eliminating Fences · ISCA 2021 |
Storage systems › buffer management
write buffering |
0.1 | 1 | 2021 | Execution Dependence Extension (EDE): ISA Support for Eliminating Fences · ISCA 2021 |
Parallel and multicore computing › transactional memory
hardware transactional memory |
0.1 | 1 | 2019 | NoMap: Speeding-Up JavaScript Using Hardware Transactional Memory · HPCA 2019 |
Memory systems
cache coherence |
0.1 | 1 | 2017 | Secure Hierarchy-Aware Cache Replacement Policy (SHARP): Defending Against Cache-Based Side Channel Attacks · ISCA 2017 |
Memory systems › cache management
cache replacement |
0.1 | 1 | 2017 | Secure Hierarchy-Aware Cache Replacement Policy (SHARP): Defending Against Cache-Based Side Channel Attacks · ISCA 2017 |
Programming languages and type systems › type systems
dynamic typing |
0.1 | 1 | 2014 | Improving JavaScript performance by deconstructing the type system · PLDI 2014 |
Methods — techniques the papers use, named apart from their topics
within-transaction optimization · 0.8reachability analysis · 0.8hardware transactional memory · 0.8dispatcher optimization · 0.6architectural support · 0.6architectural simulation · 0.5simulation-based evaluation · 0.4bloom filter · 0.4inline caching · 0.4type system deconstruction · 0.2
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2021 | Execution Dependence Extension (EDE): ISA Support for Eliminating FencesabstractFence instructions are a coarse-grained mechanism to enforce the order of instruction execution in an out-of-order pipeline. They are an overkill for cases when only one instruction must wait for the completion of one other instruction. For example, this is the case when performing undo logging in Non-Volatile Memory (NVM) systems: while the update of a variable needs to wait until the corresponding undo log entry is persisted, all other instructions can be reordered. Unfortunately, current ISAs do not provide a way to describe such an execution dependence between two instructions that have no register or memory dependences. As a result, programmers must place fences, which unnecessarily serialize many unrelated instructions.To remedy this limitation, we propose an ISA extension capable of describing these execution dependences. We call the proposal Execution Dependence Extension (EDE), and add it to Arm’s AArch64 ISA. We also present two hardware realizations of EDE that enforce execution dependences at different stages of the pipeline: one in the issue queue (IQ) and another in the write buffer (WB). We implement IQ and WB in a simulator and test them with several NVM applications. Overall, by using EDE with IQ and WB rather than fences, we attain average workload speedups of 18% and 26%, respectively. Thomas Shull, Ilias Vougioukas, Nikos Nikoleris, Wendy Elsasser, Josep Torrellas |
ISCA | 1 |
| 2021 | UniHeap: managing persistent objects across managed runtimes for non-volatile memoryabstractByte-addressable, non-volatile memory (NVM) is emerging as a promising technology. To facilitate its wide adoption, employing NVM in managed runtimes like JVM has proven to be an effective approach (i.e., managed NVM). However, such an approach is runtime specific, it lacks a generic abstraction across different managed languages. Similar to the well-known filesystem primitives that allow diverse programs to access the same file via the block I/O interface, managed NVM deserves the same system-wide property for persistent objects across managed runtimes with low overhead. Daixuan Li, Benjamin Reidys, Jinghan Sun, Thomas Shull, Josep Torrellas, Jian Huang 0006 |
SYSTOR | 4 |
| 2020 | P-INSPECT: Architectural Support for Programmable Non-Volatile Memory FrameworksabstractThe availability of user-friendly programming frameworks is key to the success of Non-Volatile Memory (NVM). Unfortunately, most current NVM frameworks rely heavily on user intervention to mark persistent objects and even persistent writes. This not only complicates NVM programming, but also introduces potential bugs. To address these issues, researchers have proposed Persistence by Reachability frameworks, which require minimal user intervention. However, these frameworks are slow because their runtimes have to perform checks at program load/store operations, and move data structures between DRAM and NVM during program execution. In this paper, we introduce P-inspect, a novel hardware architecture targeted to speeding up persistence by reachability NVM programming frameworks. P-inspect uses bloom-filter hardware to perform various checks in a transparent and efficient manner. It also provides hardware for low-overhead persistent writes. Our simulation-based evaluation running a state-of-the-art persistence by reachability framework shows that P-inspect retains programmability and eliminates most of the overhead. We use real-world applications to demonstrate that, on average, P-inspect reduces an application's number of executed instructions by 26% and the execution time by 16%-delivering similar performance to an ideal runtime that has no persistence by reachability overhead. Apostolos Kokolis, Thomas Shull, Jian Huang 0006, Josep Torrellas |
MICRO | 2 |
| 2019 | NoMap: Speeding-Up JavaScript Using Hardware Transactional MemoryabstractScripting languages' inferior performance stems from compilers lacking enough static information. To address this limitation, they use JIT compilers organized into multiple tiers, with higher tiers using profiling information to generate high-performance code. Checks are inserted to detect incorrect assumptions and, when a check fails, execution transfers to a lower tier. The points of potential transfer between tiers are called Stack Map Points (SMPs). They require a consistent state in both tiers and, hence, limit code optimization across SMPs in the higher tier. This paper examines the code generated by a state-of-theart JavaScript compiler and finds that the code has a high frequency of SMPs. These SMPs rarely cause execution to transfer to lower tiers. However, both the optimization-limiting effect of the SMPs, and the overhead of the SMP-guarding checks contribute to scripting languages' low performance. To tackle this problem, we extend the compiler to generate hardware transactions around SMPs, and perform simple within-transaction optimizations enabled by transactions. We target emerging lightweight HTM systems and call our changes NoMap. We evaluate NoMap on the SunSpider and Kraken suites. We find that NoMap lowers the instruction count by an average of 14.2% and 11.5%, and the execution time by an average of 16.7% and 8.9%, for SunSpider and Kraken, respectively. Thomas Shull, Jiho Choi, María Jesús Garzarán, Josep Torrellas |
HPCA | 1 |
| 2019 | Reusable inline caching for JavaScript performanceabstractJavaScript performance is paramount to a user’s browsing experience. Browser vendors have gone to great lengths to improve JavaScript’s steady-state performance. This has led to sophisticated web applications. However, as users increasingly expect instantaneous page load times, another important goal for JavaScript engines is to attain minimal startup times. Jiho Choi, Thomas Shull, Josep Torrellas |
PLDI | 2 |
| 2019 | AutoPersist: an easy-to-use Java NVM framework based on reachabilityabstractByte-addressable, non-volatile memory (NVM) is emerging as a revolutionary memory technology that provides persistency, near-DRAM performance, and scalable capacity. To facilitate its use, many NVM programming models have been proposed. However, most models require programmers to explicitly specify the data structures or objects that should reside in NVM. Such requirement increases the burden on programmers, complicates software development, and introduces opportunities for correctness and performance bugs. Thomas Shull, Jian Huang 0006, Josep Torrellas |
PLDI | 1 |
| 2019 | QuickCheck: using speculation to reduce the overhead of checks in NVM frameworksabstractByte addressable, Non-Volatile Memory (NVM) is emerging as a revolutionary technology that provides near-DRAM performance and scalable memory capacity. To facilitate the usability of NVM, new programming frameworks have been proposed to automatically or semi-automatically maintain crash-consistent data structures, relieving much of the burden of developing persistent applications from programmers. Thomas Shull, Jian Huang 0006, Josep Torrellas |
VEE | 1 |
| 2018 | Biased reference counting: minimizing atomic operations in garbage collectionabstractReference counting (RC) is one of the two fundamental approaches to garbage collection. It has the desirable characteristics of low memory overhead and short pause times, which are key in today's interactive mobile platforms. However, RC has a higher execution time overhead than its counterpart, tracing garbage collection. The reason is that RC implementations maintain per-object counters, which must be continually updated. In particular, the execution time overhead is high in environments where low memory overhead is critical and, therefore, non-deferred RC is used. This is because the counter updates need to be performed atomically. Jiho Choi, Thomas Shull, Josep Torrellas |
PACT | 2 |
| 2017 | ShortCut: Architectural Support for Fast Object Access in Scripting LanguagesabstractThe same flexibility that makes dynamic scripting languages appealing to programmers is also the primary cause of their low performance. To access objects of potentially different types, the compiler creates a dispatcher with a series of if statements, each performing a comparison to a type and a jump to a handler. This induces major overhead in instructions executed and branches mispredicted. Jiho Choi, Thomas Shull, María Jesús Garzarán, Josep Torrellas |
ISCA | 2 |
| 2017 | Secure Hierarchy-Aware Cache Replacement Policy (SHARP): Defending Against Cache-Based Side Channel AttacksabstractIn cache-based side channel attacks, a spy that shares a cache with a victim probes cache locations to extract information on the victim's access patterns. For example, in evict+reload, the spy repeatedly evicts and then reloads a probe address, checking if the victim has accessed the address in between the two operations. While there are many proposals to combat these cache attacks, they all have limitations: they either hurt performance, require programmer intervention, or can only defend against some types of attacks. Mengjia Yan 0001, Bhargava Gopireddy, Thomas Shull, Josep Torrellas |
ISCA | 3 |
| 2014 | Improving JavaScript performance by deconstructing the type systemabstractIncreased focus on JavaScript performance has resulted in vast performance improvements for many benchmarks. However, for actual code used in websites, the attained improvements often lag far behind those for popular benchmarks. Wonsun Ahn, Jiho Choi, Thomas Shull, María Jesús Garzarán, Josep Torrellas |
PLDI | 3 |