A 1V 56.07dB SNDR 10MHz bandwidth digital slope ADC based on Preset Bidirectional-Shifting Technique is presented. With the proposed Preset Bidirectional-Shifting Technique, the number and conversion time are decreased impressively. Under low input frequency, the structure can achieve high resolution and high speed. Moreover, passive noise-shaping is used to implement an on-chip correction for the comparator latency. The proposed ADC is simulated in a 55nm CMOS process, achieving an SNDR of 56.07dB and consuming 941μW with a 1V supply. The simulation achieved a Schreier FoM of l56.33dB.

Machine learning (ML) lifecycle is a cyclic process to build an efficient ML system. Though a lot of commercial and community (non-commercial) frameworks have been proposed to streamline the major stages in the ML lifecycle, they are normally overqualified and insufficient for an ML system in its nascent phase. Driven by real-world experience in building and maintaining ML systems, we find that it is more efficient to initialize the major stages of ML lifecycle first for trial and error, followed by the extension of specific stages to acclimatize towards more complex scenarios. For this, we introduce a simple yet flexible framework, MLife, for fast ML lifecycle initialization. This is built on the fact that data flow in MLife is in a closed loop driven by badcases, especially those which impact ML model performance the most but also provide the most value for further ML model development - a key factor towards enabling enterprises to fast track their ML capabilities.