A critical activity during electrical testing for High-Speed Serial l/O is the search for optimal Tx equalization settings that yield the cleanest eye diagram possible. Typical practices consist of performing an exhaustive grid search over two variables to define the best solution region, known as the pre-cursor and the post-cursor. This work introduces a methodology to obtain a precise approximation to the optimal equalization values based on the artificial bee colony (ABC) heuristic optimization algorithm. This algorithm explores the solution space with fewer combinations than the typically used procedure. In this work we demonstrate experimentally that the ABC algorithm converges to the solution region of the equalization settings in 36% of the time needed by a grid search. The algorithm was tested on PCIe Gen 5, but lower speed PCIe generations and other interfaces subject to Tx equalization could benefit from these optimization tools, e.g. CXL, UPI, DMI, etc.

Post-Silicon system margin validation consumes a significant amount of time and resources. To overcome this, a reduced validation plan for derivative products has previously been used. However, a certain amount of validation is still needed to avoid escapes, which is prone to subjective bias by the validation engineer comparing a reduced set of derivative validation data against the base product data. Machine Learning techniques allow to perform automatic decisions based on already available historical data. In this work, we present an efficient methodology implemented with Machine Learning to make an automatic risk assessment decision for derivative products, considering a large set of parameters obtained from the base product. The proposed methodology yields a high performance on the risk assessment decision, which translates into a significant reduction in time, effort, and resources.

As microprocessor design scales to the 10-nm technology and beyond, traditional pre- and post-silicon validation techniques are unsuitable to get a full system functional coverage. Physical complexity and extreme technology process variations severely limits the effectiveness and reliability of presilicon validation techniques. This scenario imposes the need of sophisticated post-silicon validation approaches to consider complex electromagnetic phenomena and large manufacturing fluctuations observed in actual physical platforms. One of the major challenges in electrical validation of high-speed input/output (HSIO) links in modern computer platforms lies in the physical layer (PHY) tuning process, where equalization techniques are used to cancel undesired effects induced by the channels. Current industrial practices for PHY tuning in HSIO links are very time consuming since they require massive laboratory measurements. An alternative is to use machine learning techniques to model the PHY, and then perform equalization using the resultant surrogate model. In this paper, a metamodeling approach based on neural networks is proposed to efficiently simulate the effects of a receiver equalizer PHY tuning settings. We use several design of experiments techniques to find a neural model capable of approximating the real system behavior without requiring a large amount of actual measurements. We evaluate the models performance by comparing with measured responses on a real server HSIO link.

This paper presents an enhanced methodology to validate High Speed I/O links. The methodology outlines a stress method selection process, statistical techniques to optimize volume data collection as well as a method to determine when to perform UPM calculations.